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BT8110

High-Capacity ADPCM Processor

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1.0 Product Description

1.2 Pin Descriptions

Bt8110/8110B

High-Capacity ADPCM Processor

Table 1-4. Bt8110/8110B Hardware Signal Definitions (1 of 2)

Pin Label

Signal Name

I/O

Definition

CLOCK

Clock

I The system clock provided to the Bt8110/8110B. Maximum clock

frequency is 16.5 MHz, and it must have minimum high and low

periods of 27 ns (duty cycle of 45% to 55% at 16.5 MHz, or 22%

to 78% at 8.192 MHz).

SYNC

Synchronization

I Provides input and output synchronization.

RESET(1)

Reset

I Selects the algorithm reset function per ANSI T1.303-1989 and

ITU-T G.726.

ADPCM_STB ADPCM Strobe

O Active when the parallel ADPCM inputs and outputs are enabled in

interleaved mode, and is active for both PCM inputs and ADPCM

outputs in encoder mode. This pin is disabled in decoder mode.

PCM_STB

PCM Strobe

O Active when the parallel PCM inputs and outputs are enabled in

interleaved mode, and is active for both ADPCM inputs and PCM

outputs in decoder mode. This pin is disabled in encoder mode.

SERIAL_IN

Serial Data Input

I This pin has multiplexed PCM and ADPCM signals in interleaved

mode; PCM signals for encoder mode, and ADPCM signals for

decoder mode.

SERIAL_OUT Serial Data Output

O This pin has multiplexed PCM and ADPCM signals in interleaved

mode; ADPCM signals for encoder mode, and PCM signals for

decoder mode.

PSIGEN

Parallel Signal Enable

I A control signal that enables parallel inputs. Does not affect parallel

outputs (D[7:0]), which are always available. On the Bt8110B, this

signal has extra functionality (see note in Section 2.2.1.1).

PSIG[7:0]

Parallel Signal Input

I The parallel input data bus. The most significant bit (sign bit for

PCM, I1 for ADPCM) appears on PSIG[7]. This input bus is also

used to indicate ADPCM word length when embedded decoding is

performed. When serial inputs are used, these inputs should be left

unconnected (internal pull-down resistors included) except as

required for embedded decoding.

D[7:0]

Parallel Signal Output/

ROM Data Input

I/O On the Bt8110, these signals are inputs, accepting data from the

external lookup table ROM. The data on these pins also provides

parallel PCM and ADPCM output functionality for the Bt8110. On

the Bt8110B, these signals are outputs when internal ROM is used.

D[7] is the most significant bit of the PCM and ADPCM data.

MICREN(1)

Microprocessor Enable I Active high input that selects per-channel control via a

microprocessor interface.

CS(1)

Chip Select

I Active high input that enables write operations to the

Bt8110/8110B. In hardware mode this pin enables transparent

operation.

WR*(1)

Write*

I Active low input that performs the write operation to the

Bt8110/8110B. In hardware mode this pin enables A-law PCM

coding (low for µ-law).

ALE(1)

µP Address Latch

Enable.

I ALE is a microprocessor-generated signal that causes the

Bt8110/8110B to latch in the address on the address/data bus. ALE

is active high with the address being latched on the falling edge of

the signal. In hardware mode this pin becomes an optional code

input.

AD[6:0]

µP Address/Data Bus

I Microprocessor 7-bit address and data bus.

1-10

Conexant

100060C

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