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BR34E02-3 View Datasheet(PDF) - ROHM Semiconductor

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BR34E02-3 Datasheet PDF : 33 Pages
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BR34E02-3
Datasheet
S
W
T
R
A
I
R
SLAVE
T
T
ADDRESS E
W ORD
ADDRESS
SDA
L IN E
011 0 011
*
**
RA
A
/C
C
WP
WK
K
DATA
S
T
O
P
*
A
C
K
*:DO N’T CARE
Figure 40. Clear Write Protect Cycle
(3) Clear Write Protect Cycle
(a) Clear Write Protect command can cancel write protection block which is set by set write Protect command.
When these commands are carried out, WP pin must be OPEN or GND.
(b) Clear Write Protect command needs tWR from stop condition same as Byte Write and Page Write, during tWR,
input command is canceled.
(c) Refer to Page14 about reply of ACK in each protect state.
Software Reset
Software reset is executed to avoid malfunction after power on and during command input. Software reset has several
kinds and 3 kinds of them are shown in the figure below. (Refer to Figure 41.-(a), Figure 41.-(b), and Figure 41.-(c).) Within
the dummy clock input area, the SDA bus is released ('H' by pull up) and ACK output and read data '0' (both 'L' level) may
be output from EEPROM. Therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading to
instantaneous power failure of system power source or influence upon devices.
SCL
SDA
SD
DUMMY CLOCK x 14
START x 2
12
13 14
COMMAND
COMMAND
Figure 41-(a). DUMMY CLOCK x 14 + START + START
SCL
SDA
SD
START
1
DUMMY CLOCK x 9
START
2
89
COMMAND
COMMAND
Figure 41-(b). START + DUMMY CLOCK x 9 + START
SCL
SDA
SD
START x 9
タト
1 23
7 89
Figure 41-(c). START x 9
COMMAND
COMMAND
* COMMAND starts with start condition.
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TSZ2211115001
18/30
TSZ02201-0R2R0G100520-1-2
25.Feb.2013 Rev.002
 

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