H1A424M167 View Datasheet(PDF) - Hynix Semiconductor
Part Name
Description
View to exact match
H1A424M167 Datasheet PDF : 47 Pages
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Hyundai Electronics Industries Co., Ltd.
H1A424M167
l Microcontroller Bus Timing
Time
Description
Min
Typ
Max
Tcs Chip Select setup time
0
-
-
Tas Address setup time
10
-
-
Tah Address hold time
5
-
-
Twrh Write data hold time
5
-
-
Tiop IOW,IOR period time
1
-
-
Tds Data setup time
5
-
-
(1) This is ISP Clock ; Typically, MCLK/3(VGA CIS), MCLK/6(CIF CIS)
Units
ns
ns
ns
ns
(1)clk
ns
9.3.3. Serial Interface Control Timing
stop start
SDATA
Tr
Tbuf
Tlow
Tf
start
stop
Thd;sta
SCLK
Thd;sta
Thd;dat Thigh Tsu;dat Tsu;sta Tsu;sto
l Serial Interface Timing
Time
Description
Fscl
SCL clock frequency
Tbuf Bus free time between a STOP and START
condition
Thd;sta Hold time START condition
Tlow LOW period of the SCL clock
Thigh HIGH period of the SCL clock
Tsu;sta Setup time for a repeated START condition
Thd;dat Data hold time
Tsu;dat Data setup time
Tr
Rise time of both SDA and SCL signals
Min Typ Max Units
0
- 400 KHz
1.3
-
-
µs
0.6
-
-
µs
1.3
-
-
µs
0.6
-
-
µs
0.6
-
-
µs
0
-
0.9
µs
100
-
-
ns
20
- 300 ns
+ 0.1Cb
1999 October 11
Page 44
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