datasheetbank_Logo
Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

AT89C5131 View Datasheet(PDF) - Atmel Corporation

Part Name
Description
View to exact match
AT89C5131 Datasheet PDF : 176 Pages
First Prev 21 22 23 24 25 26 27 28 29 30 Next Last
Registers
Table 28. CKCON0 (S:8Fh)
Clock Control Register 0
7
6
5
4
3
2
1
0
-
WDX2
PCAX2
SIX2
T2X2
T1X2
T0X2
X2
Bit
Bit Number Mnemonic Description
7
-
Reserved
The value read from this bit is always 0. Do not set this bit.
Watchdog Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
6
WDX2 this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Programmable Counter Array Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
5
PCAX2 this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART Clock (Mode 0 and 2)
This control bit is validated when the CPU clock X2 is set. When X2 is low,
4
SIX2 this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer2 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
3
T2X2 this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer1 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
2
T1X2 this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Timer0 Clock
This control bit is validated when the CPU clock X2 is set. When X2 is low,
1
T0X2 this bit has no effect.
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
System Clock Control bit
0
X2
Clear to select 12 clock periods per machine cycle (STD mode, FCPU = FPER =
FOSC/2).
Set to select 6 clock periods per machine cycle (X2 mode, FCPU = FPER = FOSC).
Reset Value = 0000 0000b
22 AT89C5131
4136B–USB–09/03
 

Share Link: 

datasheetbank.com [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]