AT88SC153 View Datasheet(PDF) - Atmel Corporation

Part Name

Description

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AT88SC153

3 x 64 x 8 Secure Memory with Authentication

Atmel Corporation 

AT88SC153

Identification Number

(Nc)

Cryptogram (Ci)

Secret Seed (Gc)

Memory Test Zone

Password Set

Device Configuration

Register

Program Only (PGO): If enabled (PGO = “0”), data within the zone may be changed

from “1” to “0” but never from “0” to “1”.

An identification number with up to 56 bits is defined by the issuer and should be unique

for each device.

The 56-bit cryptogram is generated by the internal random generator and modified after

each successful verification of the cryptogram by the chip, on host request. The initial

value, defined by the issuer, is diversified as a function of the identification number. The

64 bits used in the authentication protocol consist of the 56-bit cryptogram and the 8-bit

Authentication Attempts Counter (AAC). Note that any change in the AAC status will

change Ci for the next authentication attempt.

The 64-bit secret seed, defined by the issuer, is diversified as a function of the identifica-

tion number.

The memory test zone is an 8-bit free access zone for memory and protocol test.

The password set consists of two sets of two 24-bit passwords for read and write opera-

tions, defined by the issuer. The write password allows modification of the read and

write passwords of the same set. By default, Password 1 is selected for all user zones.

Secure Code: The secure code is a 24-bit password defined by Atmel and is different

for each card manufacturer. The Write 1 Password is used as the secure code until the

personalization is over (PER = 0).

Attempts Counters: There are four 8-bit password attempts counters (PACs), one for

each password, and one other 8-bit attempts counter for the authentication protocol

(AAC). The attempts counters limit the number of consecutive incorrect code presenta-

tions allowed (currently four).

This 8-bit register allows the issuer to select the device configuration options (active-

low) shown in Figure 7.

Table 7. Device Configuration Options

Bit 7

SME

Bit 6

UCR

Bit 5

UAT

Bit 4

ETA

Bit 3

CS3

Bit 2

CS2

Bit 1

CS1

Bit 0

CS0

Programmable Chip Select (CS0–CS3): The four most significant bits (b4–b7) of every

command comprise the chip select address. All AT88SC153 devices will respond to the

default chip select address of $B (1011). Each device will also respond to a second chip

select address programmed into CS0–CS3 of the device configuration register. By pro-

gramming each device to a unique chip select address, it is possible to connect up to 15

devices on the same serial data bus. The Write EEPROM and Verify Password com-

mands can be used globally to all devices sharing the bus by using the default chip

select address $B.

Eight Trials Allowed (ETA): If enabled (ETA = “0”), the ETA extends the trials limit to

eight incorrect presentations allowed (passwords or authentication). If disabled (ETA =

“1”), the PAC and AAC will allow only four incorrect attempts.

7

1016D–SMEM–04/04

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