AT52BC1661A View Datasheet(PDF) - Atmel Corporation
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AT52BC1661A Datasheet PDF : 34 Pages
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AT52BC1661A(T) [Preliminary]
must be used as shown in the “Command Definition in Hex” table. Data bit D1 must be zero
during the fourth bus cycle. All other data bits during the fourth bus cycle are don’t cares. To
determine whether block B is locked out, the Product ID Entry command is given followed by a
read operation from address 80H. If data bit D1 is zero, block B is locked. If data bit D1 is one,
block B can be reprogrammed. Please see the “Flash Protection Register Addressing Table”
on page 13 for the address locations in the protection register. To read the protection register,
the Product ID Entry command is given followed by a normal read operation from an address
within the protection register. After determining whether block B is protected or not, or reading
the protection register, the Product ID Exit command must be given prior to performing any
other operation.
RDY/BUSY: For the 16-Mbit Flash, an open-drain READY/BUSY output pin provides another
method of detecting the end of a program or erase operation. RDY/BUSY is actively pulled low
during the internal program and erase cycles and is released at the completion of the cycle.
The open-drain connection allows for OR-tying of several devices to the same RDY/BUSY
line. Please see “Status Bit Table” on page 12 for more details.
HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against
inadvertent programs to the device in the following ways: (a) VCC sense: if VCC is below 1.8V
(typical), the program function is inhibited. (b) VCC power-on delay: once VCC has reached the
VCC sense level, the device will automatically time out 10 ms (typical) before programming. (c)
Program inhibit: holding any one of OE low, CE high or WE high inhibits program cycles. (d)
Program inhibit: VPP is less than VILPP. (e) VPP power-on delay: once VPP has reached 1.65V,
program and erase operations are inhibited for 100 ns.
INPUT LEVELS: While operating with a 2.7V to 3.3V power supply, the address inputs and
control inputs (OE, CE and WE) may be driven from 0 to 5.5V without adversely affecting the
operation of the device. The I/O lines can only be driven from 0 to VCC + 0.3V.
9
3455A–STKD–11/04
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