AT34C02_07 View Datasheet(PDF) - Atmel Corporation

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AT34C02_07

Two-wire Serial EEPROM with Permanent Software Write Protect

Atmel Corporation 

AT34C02

Device Addressing

Write Operations

The 2K EEPROM device requires an 8-bit device address word following a start condi-

tion to enable the chip for a read or write operation (see Figure 8 on page 12).

The device address word consists of a mandatory one-zero sequence for the first four

most-significant bits (1010) for normal read and write operations and 0110 for writing to

the write protect register.

The next 3 bits are the A2, A1 and A0 device address bits for the AT34C02 EEPROM.

These 3 bits must compare to their corresponding hard-wired input pins.

The eighth bit of the device address is the read/write operation select bit. A read opera-

tion is initiated if this bit is high and a write operation is initiated if this bit is low.

Upon a compare of the device address, the EEPROM will output a zero. If a compare is

not made, the chip will return to a standby state. The device will not acknowledge if the

write protect register has been programmed and the control code is 0110.

BYTE WRITE: A write operation requires an 8-bit data word address following the

device address word and acknowledgment. Upon receipt of this address, the EEPROM

will again respond with a zero and then clock in the first 8-bit data word. Following

receipt of the 8-bit data word, the EEPROM will output a zero and the addressing

device, such as a microcontroller, must terminate the write sequence with a stop condi-

tion. At this time the EEPROM enters an internally-timed write cycle, tWR, to the

nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will

not respond until the write is complete (see Figure 9 on page 12).

The device will acknowledge a write command, but not write the data, if the software or

hardware write protection has been enabled. The write cycle time must be observed

even when the write protection is enabled.

PAGE WRITE: The 2K device is capable of 16-byte page write.

A page write is initiated the same as a byte write, but the microcontroller does not send

a stop condition after the first data word is clocked in. Instead, after the EEPROM

acknowledges receipt of the first data word, the microcontroller can transmit up to fifteen

more data words. The EEPROM will respond with a zero after each data word received.

The microcontroller must terminate the page write sequence with a stop condition (see

Figure 10 on page 13).

The data word address lower four bits are internally incremented following the receipt of

each data word. The higher data word address bits are not incremented, retaining the

memory page row location. When the word address, internally generated, reaches the

page boundary, the following byte is placed at the beginning of the same page. If more

than sixteen data words are transmitted to the EEPROM, the data word address will “roll

over” and previous data will be overwritten. The address “roll over” during write is from

the last byte of the current page to the first byte of the same page.

The device will acknowledge a write command, but not write the data, if the software or

hardware write protection has been enabled. The write cycle time must be observed

even when the write protection is enabled.

ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the

EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-

ing a start condition followed by the device address word. The read/write bit is

representative of the operation desired. Only if the internal write cycle has completed

will the EEPROM respond with a zero allowing the read or write sequence to continue.

9

0958Q–SEEPR–1/07

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