AT25256B-XUL View Datasheet(PDF) - Atmel Corporation
Part Name
Description
View to exact match
AT25256B-XUL Datasheet PDF : 24 Pages
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Features
• Serial Peripheral Interface (SPI) Compatible
• Supports SPI Modes 0 (0,0) and 3 (1,1)
• Data Sheet Describes Mode 0 Operation
• Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8V to 5.5V)
• 20 MHz Clock Rate (5V)
• 64-byte Page Mode and Byte Write Operation
• Block Write Protection
– Protect 1/4, 1/2, or Entire Array
• Write Protect (WP) Pin and Write Disable Instructions for Both Hardware and Software
Data Protection
• Self-timed Write Cycle (5 ms Max)
• High-reliability
– Endurance: 1 Million Write Cycles
– Data Retention: >100 Years
• Green (Pb/Halide-free/RoHS Compliant) Packaging Options
• Die Sales: Wafer Form, Waffle Pack, and Bumped Die
Description
The AT25128B/256B provides 131,072/262,144 bits of serial electrically-erasable pro-
grammable read only memory (EEPROM) organized as 16,384/32,768 words of 8 bits
each. The device is optimized for use in many industrial and commercial applications
where low-power and low-voltage operation are essential. The devices are available
in space saving 8-lead SOIC, 8-lead TSSOP, 8-ball VFBGA and 8-lead UDFN pack-
ages. In addition, the entire family is available in 1.8V (1.8V to 5.5V).
The AT25128B/256B is enabled through the Chip Select pin (CS) and accessed via a
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-
rate Erase cycle is required before Write.
Table 0-1. Pin Configurations
Pin
Function
CS
Chip Select
SCK
Serial Data Clock
SI
Serial Data Input
SO
Serial Data Output
GND
Ground
VCC
Power Supply
WP
Write Protect
HOLD
Suspends Serial Input
CS
SO
WP
GND
8-lead SOIC
1
8
2
7
3
6
4
5
VCC
HOLD
SCK
SI
8-lead TSSOP
CS 1
SO 2
8 VCC
7 HOLD
WP 3
6 SCK
GND 4
5 SI
8-lead UDFN
VCC 8
HOLD 7
1 CS
2 SO
SCK 6 3 WP
SI 5 4 GND
Bottom View
8-ball VFBGA
VCC 8
HOLD 7
1 CS
2 SO
SCK 6 3 WP
SI 5 4 GND
Bottom View
Block Write protection is enabled by programming the status register with top ¼, top ½
or entire array of write protection. Separate Program Enable and Program Disable
instructions are provided for additional data protection. Hardware data protection is
provided via the WP pin to protect against inadvertent write attempts to the status reg-
ister. The HOLD pin may be used to suspend any serial communication without
resetting the serial sequence.
SPI Serial
EEPROMS
128K (16,384 x 8)
256K (32,768 x 8)
AT25128B
AT25256B
8698B–SEEPR–3/10
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