AT24C01A-10TSI-2.7 View Datasheet(PDF) - Atmel Corporation
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AT24C01A-10TSI-2.7
Atmel Corporation
AT24C01A-10TSI-2.7 Datasheet PDF : 21 Pages
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AT24C01A/02/04/08/16
Device Addressing
The 1K, 2K, 4K, 8K and 16K EEPROM devices all require
an 8-bit device address word following a start condition to
enable the chip for a read or write operation (refer to Figure
1).
The device address word consists of a mandatory one,
zero sequence for the first four most significant bits as
shown. This is common to all the EEPROM devices.
The next 3 bits are the A2, A1 and A0 device address bits
for the 1K/2K EEPROM. These 3 bits must compare to
their corresponding hard-wired input pins.
The 4K EEPROM only uses the A2 and A1 device address
bits with the third bit being a memory page address bit. The
two device address bits must compare to their correspond-
ing hard-wired input pins. The A0 pin is no connect.
The 8K EEPROM only uses the A2 device address bit with
the next 2 bits being for memory page addressing. The A2
bit must compare to its corresponding hard-wired input pin.
The A1 and A0 pins are no connect.
The 16K does not use any device address bits but instead
the 3 bits are used for memory page addressing. These
page addressing bits on the 4K, 8K, and 16K devices
should be considered the most significant bits of the data
word address which follows. The A0, A1 and A2 pins are no
connect.
The eighth bit of the device address is the read/write opera-
tion select bit. A read operation is initiated if this bit is high
and a write operation is initiated if this bit is low.
Upon a compare of the device address, the EEPROM will
output a zero. If a compare is not made, the chip will return
to a standby state.
Write Operations
BYTE WRITE: A write operation requires an 8-bit data
word address following the device address word and
acknowledgment. Upon receipt of this address, the
EEPROM will again respond with a zero and then clock in
the first 8-bit data word. Following receipt of the 8-bit data
word, the EEPROM will output a zero and the addressing
device, such as a microcontroller, must terminate the write
sequence with a stop condition. At this time the EEPROM
enters an internally-timed write cycle, tWR, to the nonvolatile
memory. All inputs are disabled during this write cycle and
the EEPROM will not respond until the write is complete
(refer to Figure 2).
PAGE WRITE: The 1K/2K EEPROM is capable of an 8-
byte page write, and the 4K, 8K and 16K devices are capa-
ble of 16-byte page writes.
A page write is initiated the same as a byte write, but the
microcontroller does not send a stop condition after the first
data word is clocked in. Instead, after the EEPROM
acknowledges receipt of the first data word, the microcon-
troller can transmit up to seven (1K/2K) or fifteen (4K, 8K,
16K) more data words. The EEPROM will respond with a
zero after each data word received. The microcontroller
must terminate the page write sequence with a stop condi-
tion (refer to Figure 3).
The data word address lower three (1K/2K) or four (4K, 8K,
16K) bits are internally incremented following the receipt of
each data word. The higher data word address bits are not
incremented, retaining the memory page row location.
When the word address, internally generated, reaches the
page boundary, the following byte is placed at the begin-
ning of the same page. If more than eight (1K/2K) or six-
teen (4K, 8K, 16K) data words are transmitted to the
EEPROM, the data word address will “roll over” and previ-
ous data will be overwritten.
ACKNOWLEDGE POLLING: Once the internally-timed
write cycle has started and the EEPROM inputs are dis-
abled, acknowledge polling can be initiated. This involves
sending a start condition followed by the device address
word. The read/write bit is representative of the operation
desired. Only if the internal write cycle has completed will
the EEPROM respond with a zero allowing the read or
write sequence to continue.
Read Operations
Read operations are initiated the same way as write opera-
tions with the exception that the read/write select bit in the
device address word is set to one. There are three read
operations: current address read, random address read
and sequential read.
CURRENT ADDRESS READ: The internal data word
address counter maintains the last address accessed dur-
ing the last read or write operation, incremented by one.
This address stays valid between operations as long as the
chip power is maintained. The address “roll over” during
read is from the last byte of the last memory page to the
first byte of the first page. The address “roll over” during
write is from the last byte of the current page to the first
byte of the same page.
Once the device address with the read/write select bit set
to one is clocked in and acknowledged by the EEPROM,
the current address data word is serially clocked out. The
microcontroller does not respond with an input zero but
does generate a following stop condition (refer to Figure 4).
RANDOM READ: A random read requires a “dummy” byte
write sequence to load in the data word address. Once the
device address word and data word address are clocked in
and acknowledged by the EEPROM, the microcontroller
must generate another start condition. The microcontroller
now initiates a current address read by sending a device
address with the read/write select bit high. The EEPROM
acknowledges the device address and serially clocks out
7
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