AD8303AR View Datasheet(PDF) - Analog Devices
Part Name
Description
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AD8303AR Datasheet PDF : 16 Pages
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SPECIFICATIONS
+5 V OPERATION (@ VDD = +5 V ؎ 10%, –40؇C ≤ TA ≤ +85؇C, unless otherwise noted)
AD8303
Parameter
Symbol Condition
Min Typ1 Max Units
STATIC PERFORMANCE
Resolution2
Relative Accuracy2
Differential Nonlinearity2
Differential Nonlinearity2
Zero-Scale Error
Full-Scale Voltage3
Full-Scale Tempco3, 4
N
INL
DNL
DNL
VZSE
VFS
TCVFS
ANALOG OUTPUTS
Output Current
Output Resistance to GND
Capacitive Load4
IOUT
ROUT
CL
REFERENCE OUTPUT
Output Voltage
VREF
LOGIC INPUTS
Logic Input Low Voltage
VIL
Logic Input High Voltage
VIH
Input Leakage Current
IIL
Input Capacitance4
CIL
INTERFACE TIMING SPECIFICATIONS4, 5
Clock Width High
Clock Width Low
Load Pulse Width
Data Setup
Data Hold
Reset Pulse Width
Load Setup
Load Hold
Select
Deselect
tCH
tCL
tLDW
tDS
tDH
tRS
tLD1
tLD2
tCSS
tCSH
AC CHARACTERISTICS4
Voltage Output Settling Time6
tS
Voltage Output Settling Time6
tS
Shutdown Recovery Time
tSDR
Output Slew Rate
SR
DAC Glitch
Q
Digital Feedthrough
Q
Monotonic, TA = +25°C
Monotonic
Data = 000H
Data = FFFH
Data = 800H, ∆VOUT < 3 mV
Data = 000H
No Oscillation
Load > 1 MΩ
To ±0.1% of Full Scale
To ±1 LSB of Final Value5
To ±0.1% of Full Scale
Data = 000H to FFFH to 000H
SUPPLY CHARACTERISTICS
Power Supply Range
Shutdown Supply Current
Positive Supply Current7
Power Dissipation
Power Supply Sensitivity
VDD RANGE
IDD_SD
IDD
PDISS
PSS
DNL < ±1 LSB
SHDN = 0, No Load, VIL = 0 V, TA = +25°C
VDD = 5 V, VIL = 0 V, No Load
VDD = 5 V, VIL = 0 V, No Load
∆VDD = ± 10%
12
–2
–3/4
–1
2.039
±1/2 +2
±1/4 +3/4
±1/2 +1
1.25 +4.5
2.0475 2.056
16
Bits
LSB
LSB
LSB
mV
Volts
ppm/°C
±3 mA
30
Ω
500
pF
1
V
0.8 V
2.4
V
10 µA
10 pF
30
ns
30
ns
30
ns
15
ns
15
ns
30
ns
15
ns
30
ns
30
ns
30
ns
4
µs
12
µs
10
µs
2
V/µs
15
nV s
15
nV s
2.7 3.0 5.5 V
0.02 1
µA
2.1 3.4 mA
10.5 17 mW
0.001 0.004 %/%
NOTES
1Typical readings represent the average value of room temperature operation.
21 LSB = 0.5 mV for 0 V to +2.0475 V output range. The first two codes (000 H, 001H) are excluded from the linearity error measurement.
3Includes internal voltage reference error.
4These parameters are guaranteed by design and not subject to production testing.
5All input control signals are specified with tR = tF = 2 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground.
7See Figure 6 for a plot of incremental supply current consumption as a function of the digital input voltage levels.
Specifications subject to change without notice.
REV. 0
–3–
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