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MX28F2000P View Datasheet(PDF) - Macronix International

Part NameDescriptionManufacturer
MX28F2000P 2M-BIT [256K x 8] CMOS FLASH MEMORY Macronix
Macronix International Macronix
MX28F2000P Datasheet PDF : 33 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
While the Automatic Erase algorithm is in operation,
DQ7 will read "0" until the erase operation is com-
pleted. Upon completion of the erase operation, the
data on DQ7 will read "1". The Data Polling feature is
valid after the rising edge of the second WE pulse of
two write pulse sequences.
The Data Polling feature is active during Automatic
Program/Erase algorithms.
POWER-UP SEQUENCE
The MX28F2000P powers up in the Read only mode.
In addition, the memory contents may only be altered
after successful completion of a two-step command
sequence. Power up sequence is not required.
SYSTEM CONSIDERATIONS
During the switch between active and standby condi-
tions, transient current peaks are produced on the
rising and falling edges of Chip Enable. The
magnitude of these transient current peaks is
dependent on the output capacitance loading of the
device. At a minimum, a 0.1uF ceramic capacitor (high
frequency, low inherent inductance) should be used
on each device between VCC and GND, and between
VPP and GND to minimize transient effects. In
addition, to overcome the voltage drop caused by the
inductive effects of the printed circuit board traces on
FLASH memory arrays, a 4.7uF bulk electrolytic
capacitor should be used between VCC and GND for
each eight devices. The location of the capacitor
should be close to where the power supply is con-
nected to the array.
MX28F2000P
P/N: PM0380
REV. 1.5, OCT 29, 1998
10
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