The APL5325 requires proper input capacitors to supply
surge current during stepping load transients to prevent
the input rail from dropping . Because the parasitic induc-
tor from the voltage sources or other bulk capacitors to
the VIN limit the slew rate of the surge current, place the
Input capacitors near VIN as close as possible. Input ca-
pacitors should be larger than 1µF and a minimum ce-
ramic capacitor of 1µF is necessary.
The APL5325 needs a proper output capacitor to main-
tain circuit stability and to improve transient response over
temperature and current. In order to insure the circuit
stability, the proper output capacitor value should be larger
than 2.2µF. With X5R and X7R dielectrics, 2.2µF is suffi-
cient at all operating temperatures. Large output capaci-
tor value can reduce noise and improve load-transient
response and PSRR, however, it also affects power on
issue. Equation (1) shows the relationship between the
maximum C value and the V .
= 101 −
Figure 1 shows
the curve of maximum output capacitor over the output
voltage. The output voltage range is from 0.8 to 5.5V and
the output capacitor value should under the line. Output
capacitors must be placed at the load and the ground pin
as close as possible and the impedance of the layout
must be minimized.
Output Voltage (V)
Operation Region and Power Dissipation
The APL5325 maximum power dissipation depends on
the thermal resistance and temperature difference be-
tween the die junction and ambient air. The power dissi-
pation PD across the device is:
where (T -T ) is the temperature difference between the
junction and ambient air. θ is the thermal resistance
between Junction and ambient air. Assuming the
TA=25oC and maximum TJ=160oC (typical thermal limit
threshold), the maximum power dissipation is calcu-
For normal operation, do not exceed the maximum junc-
tion temperature rating of TJ = 125 oC. The calculated power
dissipation should less than:
The GND provides an electrical connection to the ground
and channels heat away. Connect the GND to the ground
by using a large pad or a ground plane.
Figure 2 illustrates the layout. Below is a checklist for
1. Please place the input capacitors close to the VIN.
2. Ceramic capacitors for load must be placed near the
load as close as possible.
3. To place APL5325 and output capacitors near the load
is good for performance.
4. Large current paths, the bold lines in figure 2, must
have wide tracks.
5. Divider resistor R1 and R2 must be placed near the
SET as close as possible.
Copyright © ANPEC Electronics Corp.
Rev. A.1 - Nov., 2008