CAT93C4611J-25TE13 View Datasheet(PDF) -
| CAT93C4611J-25TE13 Datasheet PDF : 0 Pages | |||
CAT93CXXXX
Advanced Information
can then continue to clock in 8-bit (16-bit for x16 format)
data to be written to the next higher address. Internally,
the address pointer is incremented after each group of
eight clocks (16 clocks for x16 format). If the host
transmits more than 16 bytes (8 words for x16 format)
the address counter ‘wraps around’ and previously
transmitted data will be overwritten.
After receiving a WRITE command, address and the
data, the CS (Chip Select) pin must be deselected for a
minimum of tCSMIN. The falling edge of CS will start the
self clocking clear and data store cycle of the memory
location specified in the instruction. The clocking of the
SK pin is not necessary after the device has entered the
self clocking mode. The ready/busy status of the
CAT93CXXXX can be determined by selecting the de-
vice and polling the DO pin. Since this device features
Auto-Clear before write, it is NOT necessary to erase a
memory location before it is written into.
Figure 4. Write Instruction Timing
Erase
Upon receiving an ERASE command and address, the
CS (Chip Select) pin must be deasserted for a minimum
of tCSMIN. The falling edge of CS will start the self clocking
clear cycle of the selected memory location. The clock-
ing of the SK pin is not necessary after the device has
entered the self clocking mode. The ready/busy status of
the CAT93CXXXX can be determined by selecting the
device and polling the DO pin. Once cleared, the content
of a cleared location returns to a logical “1” state.
SK
CS
AN AN-1
DI
101
A0 DN
D0
tCS
STATUS
VERIFY
STANDBY
tSV
BUSY
tHZ
HIGH-Z
DO
READY
HIGH-Z
tEW
Figure 5. Erase Instruction Timing
SK
CS
AN AN-1
A0
DI
111
STATUS VERIFY
tCS
STANDBY
tSV
tHZ
HIGH-Z
DO
BUSY READY
HIGH-Z
tEW
Stock No. 21084-01 2/98
9-92
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