AN5195K-C
ICs for TV
s Terminal Equivalent Circuits (continued)
Pin No.
57
Equivalent circuit
4.3 V
16 kΩ
4 kΩ
270 Ω
5V
(VCC3)
3 kΩ
50 kΩ
To
ver.
count
down
57
200 Ω
R2
220 Ω
R1
330 kΩ
C1
0.33 µF
58
5V
(VCC3)
50 kΩ
Description
Vertical sync. signal clamp pin:
• Peak clamp pin in order to separate
vertical sync. signal
• Integrating amount of vertical sync.
signal itself is determined by time
constant of inside but triggering tim-
ing is determined by selecting R1
and C1 of external time constant.
• Uses with R1 > 200 kΩ
• R2 is for emitter current limiting resistor
Vertical pulse output pin:
• Negative polarity, pulse width 10 H
DC (V)
AC
f = fV
AC
Pulse
58
4.3 V
43 kΩ
0V
59
fC 56.2 kΩ 12 kΩ
9V
(VCC1)
50 µA 12 kΩ
SECAM interface pin:
• Inpu/output pin for interface with
AC+DC
AC
SECAM IC
250 mV[p-p]
13.7 kΩ
61.5 kΩ
50 k
Ω
59
To
SECAM IC
200 µA
100 µA
SECAM SECAM
detecter
• SECAM mode is made by taking the
curr. of 100 µA or more from pin 59.
• At SECAM
DC4.4 V+AC250 mV[p-p]
• At non-SECAM
DC1.1 V+AC250 mV[p-p]: 4.43 MHz
or
0 mV[p-p]
DC
4.4 V
or
1.1 V
SECAM
or 0 mV[p-p]: 3.58 MHz
60
61
100 µA
100 µA 100 µA
5V
(VCC3)
−(B−Y)
60
61
−(R−Y)
To 1HDL
Pin 60: −(B−Y) output pin:
Pin 61: −(R−Y) output pin:
• At SECAM, output circuit is off
and comes to high impedance.
• Output to 1HDL
AC
−(B−Y)
−(R−Y)
SECAM
0V
SECAM
1.5 kΩ
2.5 kΩ
1.5 kΩ
DC level
approx. 2.1 V
62
5V
37 kΩ
15 kΩ (VCC3)
VBLK
HBLK
42 kΩ
63 kΩ
BGP
62
44 kΩ
Sandcastle pulse output pin:
• Sandcastle pulse is outputted to
1HDL and SECAM IC.
AC
Pulse
4.7 V
2.4 V
24