AN5095K View Datasheet(PDF) - Panasonic Corporation
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Description
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AN5095K Datasheet PDF : 36 Pages
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AN5095K
ICs for TV
s Technical Information (continued)
• Explanation of each block (continued)
6. Jungle (continued)
3) Built-in frequency discrimination circuit: The circuit outputs the judgment results of 50 Hz/60 Hz in accor-
dance with the frequency of the vertical synchronizing signal.
(60 Hz → high)
Input frequency
45
55
65
Judgement
Hold
50 Hz
60 Hz
Hold
Output voltage
(Low)
(High)
4) The output holds the previous state when the input frequency is 45 Hz or less and 65 Hz or more, and the
output changes for the first time when judged as 50 Hz or 60 Hz for 3 consecutive vertical periods.
5) The horizontal detection circuit and X-ray protection circuit (shut-down method) are built in.
6) The screen center position is adjustable by the I2C bus. (±1.6 µs)
7) For the blue-back in a weak electric field, the stable screen image is held by the vertical trigger off mode ( I2C
bus).
7. I2C bus
1) Incorporating 14 DAC controls and 12 SWs for eliminating the need for the adjustment of set mechanism.
2) Provided with automatic increment function.
• Sub address 0 *: Automatic increment mode.
(When data are sent in regular succession, sub address changes successively and data are inputted.)
• Sub address 8 *:
(When data are sent in regular succession, data are inputted with the same sub address.)
3) I2C Bus Protocol
• Slave address: 10 001 010 (8AH)
• Slave address format
S Slave address 0
A
Sub address
A Data byte A P
Start
condition
Write Acknowledge bit
4) Sub address byte and data byte format
The description in ( ) shows the initial state.
Sub address
D7
Data byte
D6
D5 D4
D3
D2
00
(21H)
P/N
(0 → P)
PN/S
(0 → PN)
Color
01
(21H)
Ver. auto Ver. TRG
(0 → auto) (0 → normal)
Tint
02
(41H)
Ver. OSC
(0 → 50)
Brightness
03
SIF
Video
(21H)
SW
SW
Contrast
04
(81H)
Cut off R
05
(81H)
Cut off G
06
(81H)
Cut off B
Stop
condition
D1
D0
32
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