AM29LV160M View Datasheet(PDF) - Advanced Micro Devices

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AM29LV160M

16 Megabit (2 M x 8-Bit/1 M x 16-Bit) MirrorBit™ 3.0 Volt-only Boot Sector Flash Memory

Advanced Micro Devices 

Data Sheet

for erasure. Thus, both status bits are required for sector and mode information.

Refer to Table 12, on page 38 to compare outputs for DQ2 and DQ6.

Figure 8, on page 37 shows the toggle bit algorithm in flowchart form, and the

section “Reading Toggle Bits DQ6/DQ2” explains the algorithm. See also the

“DQ6: Toggle Bit I” on page 35 subsection.Figure 20, on page 48 shows the tog-

gle bit timing diagram. Figure 21, on page 49 shows the differences between DQ2

and DQ6 in graphical form.

Reading Toggle Bits DQ6/DQ2

Refer to Figure 8, on page 37 for the following discussion. Whenever the system

initially begins reading toggle bit status, it must read DQ7–DQ0 at least twice

in a row to determine whether a toggle bit is toggling. Typically, the system

would note and store the value of the toggle bit after the first read. After the

second read, the system would compare the new value of the toggle bit with

the first. If the toggle bit is not toggling, the device completed the program or

erase operation. The system can read array data on DQ7–DQ0 on the following

read cycle.

However, if after the initial two read cycles, the system determines that the toggle

bit is still toggling, the system also should note whether the value of DQ5 is high

(see the section on DQ5). If it is, the system should then determine again

whether the toggle bit is toggling, since the toggle bit may have stopped toggling

just as DQ5 went high. If the toggle bit is no longer toggling, the device success-

fully completed the program or erase operation. If it is still toggling, the device

did not complete the operation successfully, and the system must write the reset

command to return to reading array data.

The remaining scenario is that the system initially determines that the toggle bit

is toggling and DQ5 did not go high. The system may continue to monitor the tog-

gle bit and DQ5 through successive read cycles, determining the status as

described in the previous paragraph. Alternatively, it may choose to perform

other system tasks. In this case, the system must start at the beginning of the

algorithm when it returns to determine the status of the operation (top of Figure

8, on page 37).

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Am29LV160M

25974B5 January 31, 2007

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