Notes: See Tables 10 and 11 for program command sequence.
Figure 4. Program Operation
Chip Erase Command Sequence
Chip erase is a six bus cycle operation. The chip erase command sequence is ini-
tiated by writing two unlock cycles, followed by a set-up command. Two
additional unlock write cycles are then followed by the chip erase command,
which in turn invokes the Embedded Erase algorithm. The device does not require
the system to preprogram prior to erase. The Embedded Erase algorithm auto-
matically preprograms and verifies the entire memory for an all zero data pattern
prior to electrical erase. The system is not required to provide any controls or tim-
ings during these operations. Table 10, on page 31 and Table 11, on page 32
show the address and data requirements for the chip erase command sequence.
Note that the Secured Silicon Sector, autoselect, and CFI functions are unavail-
able when an erase operation is in progress.
Any commands written to the chip during the Embedded Erase algorithm are ig-
nored. Note that a hardware reset during the chip erase operation immediately
terminates the operation. The Chip Erase command sequence should be reiniti-
ated once the device returns to reading array data, to ensure data integrity.
The system can determine the status of the erase operation by using DQ7, DQ6,
DQ2, or RY/BY#. See “Autoselect Command Sequence” on page 24 for informa-
tion on these status bits. When the Embedded Erase algorithm is complete, the
device returns to reading array data and addresses are no longer latched.
25974B5 January 31, 2007