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AK93C45C View Datasheet(PDF) - Asahi Kasei Microdevices

Part Name
Description
View to exact match
AK93C45C
AKM
Asahi Kasei Microdevices AKM
AK93C45C Datasheet PDF : 16 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ASAHI KASEI
[AK93C45C/55C/65C]
WRITE
The write instruction is followed by 16 bits of data to be written into the specified address. After the
last bit of data is put on the DI pin, the CS pin must be brought low before the next rising edge of the
SK clock. This falling edge of the CS initiates the self-timed programming cycle. The DO
indicates the Busy/Ready status of the chip if the CS is brought high after a minimum of ‘tCS’.
DO=logical "0" indicates that programming is still in progress. DO=logical "1" indicates that the
register at the address specified in the instruction has been written with the new data pattern
contained in the instruction and the part is ready for a next instruction.
PE
CS
SK
DI
DO
012345
8 9 10 11
01
Start Bit
0 1 A5 A4
Op code
Hi-Z
A1 A0 D15 D14
AK93C45C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
WRITE (AK93C45C)
23 24 25 tCS
D2 D1 D0
Busy
Ready
tE/W
PE
CS
SK
DI
DO
012345
10 11 12 13
01
Start Bit
0 1 X A6
Op code
Hi-Z
A1 A0 D15 D14
AK93C55C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
WRITE (AK93C55C)
PE
CS
SK
DI
DO
012345
10 11 12 13
01
Start Bit
0 1 A7 A6
Op code
Hi-Z
A1 A0 D15 D14
AK93C65C output a logic "1" (Ready status),
if previous instruction is WRITE, PAGE WRITE, WRAL.
WRITE (AK93C65C)
DAM06E-01
-5-
25 26 27 tCS
D2 D1 D0
Busy
Ready
tE/W
X: Don't care
25 26 27 tCS
D2 D1 D0
Busy
Ready
tE/W
2005/10
 

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