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ADV7390BCPZ View Datasheet(PDF) - Analog Devices

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ADV7390BCPZ Datasheet PDF : 108 Pages
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Data Sheet
Table 64. 8-Bit 525i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled.
1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
Table 65. 8-Bit 525i YCrCb In (EAV/SAV), CVBS/Y-C Out
Subaddress Setting Description
0x17
0x02 Software reset
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x10 WLCSP required.
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xCB Pixel data valid. CVBS/Y-C (S-Video)
out. SSAF PrPb filter enabled. Active
video edge control enabled. Pedestal
enabled.
Table 66. 8-Bit 525i YCrCb In, YPrPb Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x8A
0x0C Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 67. 8-Bit 525i YCrCb In (EAV/SAV), RGB Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x02
0x10 RGB output enabled. RGB output sync
enabled.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
ADV7390/ADV7391/ADV7392/ADV7393
Table 68. 8-Bit 525i YCrCb In, RGB Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x02
0x10 RGB output enabled. RGB output sync
enabled.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. RGB out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Table 69. 10-Bit 525i YCrCb In (EAV/SAV), YPrPb Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x10 10-bit input enabled.
Table 70. 10-Bit 525i YCrCb In, YPrPb Out
Subaddress Setting Description
0x17
0x02 Software reset.
0x00
0x1C All DACs enabled. PLL enabled (16×).
0x01
0x00 SD input mode.
0x80
0x10 NTSC standard. SSAF luma filter
enabled. 1.3 MHz chroma filter enabled.
0x82
0xC9 Pixel data valid. YPrPb out. SSAF PrPb
filter enabled. Active video edge
control enabled. Pedestal enabled.
0x88
0x10 10-bit input enabled.
0x8A
0x0C
Timing Mode 2 (slave). HSYNC/VSYNC
synchronization.
Rev. G | Page 93 of 108
 

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