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ADV7392 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7392 Low Power, Chip Scale 10-Bit SD/HD Video Encoder ADI
Analog Devices ADI
ADV7392 Datasheet PDF : 96 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Input Setup Time, t114
Data Input Hold Time, t124
Control Input Setup Time, t114
Control Input Hold Time, t124
Control Output Access Time, t134
Control Output Hold Time, t144
PIPELINE DELAY5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (8×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (8×)
Component Outputs (16×)
ED1
Component Outputs (1×)
Component Outputs (4×)
Component Outputs (8×)
HD1
Component Outputs (1×)
Component Outputs (2×)
Component Outputs (4×)
RESET CONTROL
RESET Low Time
Conditions1
Min Typ Max
SD
2.1
ED/HD-SDR
2.3
ED/HD-DDR
2.3
ED (at 54 MHz)
1.7
SD
1.0
ED/HD-SDR
1.1
ED/HD-DDR
1.1
ED (at 54 MHz)
1.0
SD
2.1
ED/HD-SDR or ED/HD-DDR
2.3
ED (at 54 MHz)
1.7
SD
1.0
ED/HD-SDR or ED/HD-DDR
1.1
ED (at 54 MHz)
1.0
SD
12
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz)
10
SD
4.0
ED/HD-SDR, ED/HD-DDR, or ED (at 54 MHz) 3.5
SD oversampling disabled
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling disabled
SD oversampling enabled
ED oversampling disabled
ED oversampling disabled
ED oversampling enabled
HD oversampling disabled
HD oversampling disabled
HD oversampling enabled
68
79
67
78
69
84
41
49
46
40
42
44
100
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2 Video Data: P[15:0] for ADV7392/ADV7393 or P[7:0] for ADV7390/ADV7391.
3 Video Control: HSYNC and VSYNC.
4 Guaranteed by characterization.
5 Guaranteed by design.
Unit
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clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
ns
Rev. 0 | Page 7 of 96
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