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ADV7390BCPZ View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7390BCPZ Low Power, Chip Scale 10-Bit SD/HD Video Encoder ADI
Analog Devices ADI
ADV7390BCPZ Datasheet PDF : 96 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7390/ADV7391/ADV7392/ADV7393
DIGITAL INPUT/OUTPUT SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 5.
Parameter
Input High Voltage, VIH
Input Low Voltage, VIL
Input Leakage Current, IIN
Input Capacitance, CIN
Output High Voltage, VOH
Output Low Voltage, VOL
Three-State Leakage Current
Three-State Output Capacitance
Conditions
VIN = VDD_IO
ISOURCE = 400 μA
ISINK = 3.2 mA
VIN = 0.4 V, 2.4 V
Min
Typ
Max
Unit
2.0
V
0.8
V
±10
μA
4
pF
2.4
V
0.4
V
±1
μA
4
pF
MPU PORT TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V, PVDD = 1.71 V to 1.89 V, VAA = 2.6 V to 3.465 V, VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 6.
Parameter
MPU PORT, I2C MODE1
SCL Frequency
SCL High Pulse Width, t1
SCL Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDA, SCL Rise Time, t6
SDA, SCL Fall Time, t7
Setup Time (Stop Condition), t8
MPU PORT, SPI MODE1
SCLK Frequency
SPI_SS to SCLK Setup Time, t1
SCLK High Pulse Width, t2
SCLK Low Pulse Width, t3
Data Access Time after SCLK Falling Edge, t4
Data Setup Time prior to SCLK Rising Edge, t5
Data Hold Time after SCLK Rising Edge, t6
SPI_SS to SCLK Hold Time, t7
SPI_SS to MISO High Impedance, t8
Conditions
See Figure 15
See Figure 16
Min Typ Max Unit
0
400 kHz
0.6
μs
1.3
μs
0.6
μs
0.6
μs
100
ns
300 ns
300 ns
0.6
μs
0
10
MHz
20
ns
50
ns
50
ns
35
ns
20
ns
0
ns
0
ns
40
ns
1 Guaranteed by characterization.
Rev. 0 | Page 6 of 96
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