ADV7391 View Datasheet(PDF) - Analog Devices
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ADV7391 Datasheet PDF : 108 Pages
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Data Sheet
APPLICATIONS
Mobile handsets
Digital still cameras
Portable media and DVD players
Portable game consoles
Digital camcorders
Set-top box (STB)
Automotive infotainment (ADV7392 and ADV7393 only)
GENERAL DESCRIPTION
The ADV7390/ADV7391/ADV7392/ADV7393 are a family of
high speed, digital-to-analog video encoders on single monolithic
chips. Three 2.7 V/3.3 V, 10-bit video DACs (a single DAC for
the WLCSP package) provide support for composite (CVBS),
S-Video (Y-C), or component (YPrPb/RGB) analog outputs in
either standard definition (SD) or high definition (HD) video
formats. The single DAC WLCSP package supports CVBS
(NTSC and PAL) output only in SD resolution (see Table 2).
Optimized for low power operation, occupying a minimal
footprint, and requiring few external components, these
encoders are ideally suited to portable and power-sensitive
applications requiring TV-out functionality. Cable detection
and DAC autopower-down features ensure that power
consumption is kept to a minimum.
The ADV7390/ADV7391 have an 8-bit video input port that
supports SD video formats over an SDR interface and HD video
formats over a DDR interface. The ADV7392/ADV7393 have
a 16-bit video input port that can be configured in a variety of
ways. SD RGB input is supported.
All members of the family support embedded EAV/SAV timing
codes, external video synchronization signals, and the I2C® and
communication protocol. Table 1 and Table 2 list the video
standards directly supported by the ADV739x family.
ADV7390/ADV7391/ADV7392/ADV7393
Table 1. Standards Directly Supported by the LFCSP Packages
Active
Frame
Clock Input
Resolution I/P1 Rate (Hz) (MHz)
Standard
720 × 240 P 59.94
27
720 × 288 P 50
27
720 × 480 I 29.97
27
ITU-R
BT.601/656
720 × 576 I 25
27
ITU-R
BT.601/656
640 × 480 I 29.97
24.54
NTSC Square
Pixel
768 × 576 I 25
29.5
PAL Square
Pixel
720 × 483 P 59.94
27
SMPTE 293M
720 × 483 P 59.94
27
BTA T-1004
720 × 483 P 59.94
27
ITU-R BT.1358
720 × 576 P 50
27
ITU-R BT.1358
720 × 483 P 59.94
27
ITU-R BT.1362
720 × 576 P 50
27
ITU-R BT.1362
1920 × 1035 I 30
74.25
SMPTE 240M
1920 × 1035 I 29.97
74.1758
SMPTE 240M
1280 × 720 P
60, 50, 30, 74.25
25, 24
SMPTE 296M
1280 × 720 P
23.97,
74.1758
59.94, 29.97
SMPTE 296M
1920 × 1080 I 30, 25
74.25
SMPTE 274M
1920 × 1080 I 29.97
74.1758
SMPTE 274M
1920 × 1080 P 30, 25, 24 74.25
SMPTE 274M
1920 × 1080 P 23.98, 29.97 74.1758
SMPTE 274M
1920 × 1080 P 24
74.25
ITU-R BT.709-5
1 I = interlaced, P = progressive.
Table 2. Standards Directly Supported by the WLCSP Package
Active
Frame
Clock Input
Resolution I/P1 Rate (Hz) (MHz)
Standard
720 × 480 I 29.97
27
ITU-R
BT.601/656
720 × 576 I 25
27
ITU-R
BT.601/656
640 × 480 I 29.97
24.54
NTSC Square
Pixel
768 × 576 I 25
29.5
PAL Square
Pixel
1 I = interlaced, P = progressive.
Rev. G | Page 5 of 108
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