ADV7390/ADV7391/ADV7392/ADV7393
Data Sheet
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Y0 Y1 Y2 Y3
PIXEL PORT
Cb0 Cr0 Cb2 Cr2
a
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 14. HD-SDR, 16-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
Y OUTPUT
b
HSYNC
VSYNC
PIXEL PORT
Cb0 Y0 Cr0 Y1
a
a = AS PER RELEVANT STANDARD.
b = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING
SPECIFICATION SECTION OF THE DATA SHEET.
A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT
AFTER A TIME EQUAL TO THE PIPELINE DELAY.
Figure 15. HD-DDR, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram
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