ADV7390/ADV7391/ADV7392/ADV7393
TIMING DIAGRAMS
The following abbreviations are used in Figure 4 to Figure 11:
• t9 = clock high time
• t10 = clock low time
• t11 = data setup time
• t12 = data hold time
CLKIN
t9 t10
t12
CONTROL HSYNC
INPUTS VSYNC
Data Sheet
• t13 = control output access time
• t14 = control output hold time
In addition, see Table 35 for the ADV7390/ADV7391 pixel port
input configuration and Table 36 for the ADV7392/ADV7393
pixel port input configuration.
IN SLAVE MODE
PIXEL PORT
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
t11
CONTROL
OUTPUTS
t13
t14
Figure 4. SD Input, 8-/10-Bit 4:2:2 YCrCb, Input Mode 000
IN MASTER/SLAVE MODE
CLKIN
CONTROL
INPUTS
HSYNC
VSYNC
PIXEL PORT
PIXEL PORT
CONTROL
OUTPUTS
t9
t10
t12
Y0
Y1
Y2
Y3
Cb0
Cr0
Cb2
Cr2
t11
t13
t14
Figure 5. SD Input, 16-Bit 4:2:2 YCrCb, Input Mode 000
IN SLAVE MODE
IN MASTER/SLAVE MODE
Rev. G | Page 12 of 108