ADV7390/ADV7391/ADV7392/ADV7393
CLKIN*
t9
t10
PIXEL PORT
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
t12
t11
t12
t11
t13
CONTROL
OUTPUTS
t14
*LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2.
Figure 7. ED/HD-DDR Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 010
CLKIN
CONTROL HSYNC
INPUTS VSYNC
PIXEL PORT
t9 t10
Cb0
Y0
Cr0
Y1
Cb2
Y2
Cr2
t11
t12
t13
t14
CONTROL
OUTPUTS
Figure 8. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (HSYNC/VSYNC), Input Mode 111
CLKIN
t9 t10
PIXEL PORT
3FF
00
00
XY
Cb0
Y0
Cr0
Y1
t12
t11
t13
t14
CONTROL
OUTPUTS
Figure 9. ED (at 54 MHz) Input, 8-/10-Bit 4:2:2 YCrCb (EAV/SAV), Input Mode 111
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