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ADV7342BSTZ View Datasheet(PDF) - Analog Devices

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ADV7342BSTZ Datasheet PDF : 88 Pages
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ADV7342/ADV7343
DIGITAL TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Setup Time, t114
Data Hold Time, t124
Control Setup Time, t114
Control Hold Time, t124
Digital Output Access Time, t134
Digital Output Hold Time, t144
PIPELINE DELAY5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
ED1
Component Outputs (1×)
Component Outputs (8×)
HD1
Component Outputs (1×)
Component Outputs (4×)
Conditions1
Min Typ Max
SD
2.1
ED/HD-SDR
2.3
ED/HD-DDR
2.3
ED (at 54 MHz)
1.7
SD
1.0
ED/HD-SDR
1.1
ED/HD-DDR
1.1
ED (at 54 MHz)
1.0
SD
2.1
ED/HD-SDR or ED/HD-DDR
2.3
ED (at 54 MHz)
1.7
SD
1.0
ED/HD-SDR or ED/HD-DDR
1.1
ED (at 54 MHz)
1.0
SD
12
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
10
SD
4.0
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz) 3.5
SD oversampling disabled
68
SD oversampling enabled
67
SD oversampling disabled
78
SD oversampling enabled
84
ED oversampling disabled
41
ED oversampling enabled
46
HD oversampling disabled
40
HD oversampling enabled
44
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2 Video data: C[7:0], Y[7:0], and S[7:0].
3 Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC.
4 Guaranteed by characterization.
5 Guaranteed by design.
Unit
ns
ns
ns
ns
ns
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ns
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ns
ns
ns
ns
ns
ns
ns
ns
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clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
clock cycles
Rev. 0 | Page 7 of 88
 

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