ADV7341 View Datasheet(PDF) - Analog Devices
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ADV7341 Datasheet PDF : 88 Pages
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ADV7340/ADV7341
DIGITAL TIMING SPECIFICATIONS
VDD = 1.71 V to 1.89 V. PVDD = 1.71 V to 1.89 V. VAA = 2.6 V to 3.465 V. VDD_IO = 2.97 V to 3.63 V.
All specifications TMIN to TMAX (−40°C to +85°C), unless otherwise noted.
Table 7.
Parameter
VIDEO DATA AND VIDEO CONTROL PORT2, 3
Data Setup Time, t114
Data Hold Time, t124
Control Setup Time, t114
Control Hold Time, t124
Digital Output Access Time, t134
Digital Output Hold Time, t144
PIPELINE DELAY5
SD1
CVBS/YC Outputs (2×)
CVBS/YC Outputs (16×)
Component Outputs (2×)
Component Outputs (16×)
ED1
Component Outputs (1×)
Component Outputs (8×)
HD1
Component Outputs (1×)
Component Outputs (4×)
Conditions1
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR
ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR or ED/HD-DDR
ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD
ED/HD-SDR, ED/HD-DDR or ED (at 54 MHz)
SD oversampling disabled
SD oversampling enabled
SD oversampling disabled
SD oversampling enabled
ED oversampling disabled
ED oversampling enabled
HD oversampling disabled
HD oversampling enabled
Min Typ Max Unit
2.1
ns
2.3
ns
2.3
ns
1.7
ns
1.0
ns
1.1
ns
1.1
ns
1.0
ns
2.1
ns
2.3
ns
1.7
ns
1.0
ns
1.1
ns
1.0
ns
12 ns
10 ns
4.0
ns
3.5
ns
68
clock cycles
67
clock cycles
78
clock cycles
84
clock cycles
41
clock cycles
46
clock cycles
40
clock cycles
44
clock cycles
1 SD = standard definition, ED = enhanced definition (525p/625p), HD = high definition, SDR = single data rate, DDR = dual data rate.
2 Video data: C[9:0], Y[9:0], and S[9:0].
3 Video control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, and S_VSYNC.
4 Guaranteed by characterization.
5 Guaranteed by design.
Rev. 0 | Page 7 of 88
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