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ADV7324 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7324 Multiformat 216 MHz Video Encoder with Six NSV® 14-Bit DACs ADI
Analog Devices ADI
ADV7324 Datasheet PDF : 92 Pages
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ADV7324
TIMING SPECIFICATIONS
VAA = 2.375 V to 2.625 V, VDD = 2.375 V to 2.625 V, VDD_IO = 2.375 V to 3.6 V, VREF = 1.235 V, RSET = 3040 Ω, RLOAD = 150 Ω. All
specifications TMIN to TMAX (0°C to 70°C), unless otherwise noted.
Table 4.
Parameter
MPU PORT1
SCLOCK Frequency
SCLOCK High Pulse Width, t1
SCLOCK Low Pulse Width, t2
Hold Time (Start Condition), t3
Setup Time (Start Condition), t4
Data Setup Time, t5
SDATA, SCLOCK Rise Time, t6
SDATA, SCLOCK Fall Time, t7
Setup Time (Stop Condition), t8
RESET Low Time
Min Typ Max Unit
0
400 kHz
0.6
µs
1.3
µs
0.6
µs
0.6
µs
100
ns
300 ns
300 ns
0.6
µs
100
ns
Test Conditions
First clock generated after this period relevant for
repeated start condition
ANALOG OUTPUTS
Analog Output Delay2
7
ns
Output Skew
1
ns
CLOCK CONTROL AND PIXEL PORT3
fCLK
29.5 MHz
SD PAL square pixel mode
fCLK
81
MHz
PS/HD async mode
Clock High Time, t9
40
% of one clock cycle
Clock Low Time, t10
40
% of one clock cycle
Data Setup Time, t111
2.0
ns
Data Hold Time, t121
2.0
ns
SD Output Access Time, t13
15 ns
SD Output Hold Time, t14
5.0
ns
HD Output Access Time, t13
14 ns
HD Output Hold Time, t14
5.0
ns
PIPELINE DELAY4
63
Clock cycles
SD (2×, 16×)
76
Clock cycles
SD component mode (16×)
35
Clock cycles
PS (1×)
41
Clock cycles
PS (8×)
36
Clock cycles
HD (2×, 1×)
1 Guaranteed by characterization.
2 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of DAC output full-scale transition.
3 Data: C[9:0]; Y[9:0], S[9:0]; Control: P_HSYNC, P_VSYNC, P_BLANK, S_HSYNC, S_VSYNC, S_BLANK.
4 SD, PS = 27 MHz, HD = 74.25 MHz.
Rev. 0 | Page 8 of 92
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