ADV7320KSTZ View Datasheet(PDF) - Analog Devices

Part Name

Description

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ADV7320KSTZ

Multiformat 216 MHz Video Encoder with Six NSV® 12-Bit DACs

Analog Devices 

ADV7320/ADV7321

Y OUTPUT

P_HSYNC

P_VSYNC

P_BLANK

Y9–Y0

C9–C0

c

a

Y0 Y1 Y2 Y3

Cb0 Cr0 Cr1 Cb1

b

a AND b AS PER RELEVANT STANDARD

c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE TIMING SPECIFICATION

SECTION OF THE DATA SHEET.

A FALLING EDGE OF HSYNC IN TO THE ENCODER GENERATES A FALLING EDGE OF TRI-LEVEL SYNC ON THE OUTPUT

AFTER A TIME EQUAL TO THE PIPELINE DELAY.

Figure 15. HD 4:2:2 Input Timing Diagram

P_HSYNC

P_VSYNC

a

P_BLANK

Y9–Y0

b

a = 32 CLKCYCLES FOR 525p

a = 24 CLKCYCLES FOR 625p

AS RECOMMENDED BY STANDARD

b(MIN) = 244 CLKCYCLES FOR 525p

b(MIN) = 264 CLKCYCLES FOR 625p

Figure 16. PS 4:2:2 10-Bit Interleaved Input Timing Diagram

Cb Y Cr Y

Rev. 0 | Page 14 of 88

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