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ADV7310 View Datasheet(PDF) - Analog Devices

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ADV7310 Datasheet PDF : 84 Pages
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ADV7310/ADV7311
TIMING MODES
HD Async Timing Mode
[Subaddress 10h, Bit 3, 2]
For any input data that does not conform to the standards select-
able in input mode, Subaddress 10h, asynchronous timing mode
can be used to interface to the ADV7310/ADV7311. Timing control
signals for HSYNC, VSYNC, and BLANK have to be programmed
by the user. Macrovision and programmable oversampling rates
are not available in async timing mode.
In async mode, the PLL must be turned off [Subaddress 00h,
Bit 1 = 1].
Figures 29a and 29b show examples of how to program the
ADV7310/ADV7311 to accept a different high definition standard
other than SMPTE 293M, SMPTE 274M, SMPTE 296M, or
ITU-R BT.1358.
The following truth table must be followed when programming the
control signals in async timing mode. For standards that do not
require a tri-sync level, P_BLANK must be tied low at all times.
CLK
P_HSYNC
P_VSYNC
P_BLANK
SET ADDRESS 10h,
BIT 6 TO 1
HORIZONTAL SYNC
ACTIVE VIDEO
PROGRAMMABLE
INPUT TIMING
ANALOG
OUTPUT
81
66
66
243
1920
a
b
c
d
e
Figure 29a. Async Timing Mode—Programming Input Control Signals for SMPTE 295M Compatibility
CLK
P_HSYNC
P_VSYNC
P_BLANK
SET ADDRESS 10h,
BIT 6 TO 1
HORIZONTAL SYNC
0
1
ACTIVE VIDEO
ANALOG OUTPUT
a
b
c
d
e
Figure 29b. Async Timing Mode—Programming Input Control Signals for Bilevel Sync Signal
–34–
REV. A
 

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