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ADV7310 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7310 Multiformat 216 MHz Video Encoder with Six NSV? 12-Bit DACs ADI
Analog Devices ADI
ADV7310 Datasheet PDF : 84 Pages
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ADV7310/ADV7311
SDTV
DECODER
3
27MHz
YCrCb 10
ADV7310/
ADV7311
S_VSYNC
S_HSYNC
S_BLANK
CLKIN_A
S[9:0]
HDTV
DECODER
1080i
OR
720p
CrCb 10
Y 10
3
74.25MHz
C[9:0]
Y[9:0]
P_VSYNC
P_HSYNC
P_BLANK
CLKIN_B
Figure 25. Simultaneous HD and SD Input
If in simultaneous SD/HD input mode the two clock phases
differ by less than 9.25 ns or more than 27.75 ns, the CLOCK
ALIGN bit [Address 01h Bit 3] must be set accordingly. If the
application uses the same clock source for both SD and PS, the
CLOCK ALIGN bit must be set since the phase difference
between both inputs is less than 9.25 ns.
CLKIN_A
CLKIN_B
tDELAY Ͻ 9.25ns OR
tDELAY Ͼ 27.75ns
Figure 26. Clock Phase with Two Input Clocks
Progressive Scan at 27 MHz (Dual Edge) or 54 MHz
Address[01h] : Input Mode 100 or 111, Respectively
YCrCb progressive scan data can be input at 27 MHz or 54 MHz.
The input data is interleaved onto a single 8-/10-bit bus and is
input on Pins Y9–Y0. When a 27 MHz clock is supplied, the data
is clocked in on the rising and falling edge of the input clock and
CLOCK EDGE [Address 0x01, Bit 1] must be set accordingly.
The following figures show the possible conditions: (a) Cb data
on the rising edge and (b) Y data on the rising edge.
CLKIN_B
Y9–Y0
3FF
00
00
XY
Cb0 Y0
Cr0
Y1
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 0 IN THIS CASE.
Figure 27a. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
CLKIN_B
Y9–Y0
3FF
00
00
XY
Y0
Cb0
Y1 Cr0
CLOCK EDGE ADDRESS 0x00 BIT 1 SHOULD BE SET TO 1 IN THIS CASE.
Figure 27b. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
CLKIN
PIXEL INPUT
DATA
3FF 00
00
XY Cb0 Y0 Cr0 Y1
WITH A 54 MHz CLOCK, THE DATA IS LATCHED ON EVERY RISING EDGE.
Figure 27c. Input Sequence in PS Bit Interleaved
Mode (EAV/SAV)
MPEG2
DECODER
YCrCb 27MHz OR 54MHz
ADV7310/
ADV7311
CLKIN_A
INTERLACED
TO
YCrCb 10
PROGRESSIVE
3
Y[9:0]
P_VSYNC
P_HSYNC
P_BLANK
Figure 28. 1 ϫ 10-Bit PS at 27 MHz or 54 MHz
Table I provides an overview of all possible input configurations.
REV. A
–31–
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