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ADV7310 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7310 Multiformat 216 MHz Video Encoder with Six NSV™ 12-Bit DACs ADI
Analog Devices ADI
ADV7310 Datasheet PDF : 84 Pages
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ADV7310/ADV7311
SR7–
SR0
00h
Register
Power Mode
Register
01h Mode Select
Register
Bit Description
Bit 7
Sleep Mode. With this
control enabled, the
current consumption is
reduced to µA level. All
DACs and the internal
PLL cct are disabled. I2C
registers can be read from
and written to in Sleep
Mode.
PLL and Oversampling
Control. This control
allows the internal PLL cct
to be powered down and
the over-sampling to be
switched off.
DAC F: Power On/Off
DAC E: Power On/Off
DAC D: Power On/Off
DAC C: Power On/Off
DAC B: Power On/Off
DAC A: Power On/Off 0
1
BTA T-1004 or BT.1362
Compatibility
Clock Edge
Reserved
Clock Align
Input Mode
Y/S Bus Swap
0
1
Bit 6
0
1
0
0
0
0
1
1
1
1
Bit 5
0
1
0
0
1
1
0
0
1
1
Bit 4
0
1
0
1
0
1
0
1
0
1
Bit 3
0
1
0
1
Bit 2
0
1
0
Bit 1
0
1
0
1
Bit 0
0
1
0
1
Register Setting
Sleep Mode off
Sleep Mode on
Register Reset Values
(Shaded)
FCh
PLL on
PLL off
DAC F off
DAC F on
DAC E off
DAC E on
DAC D off
DAC D on
DAC D off
DAC C on
DAC B off
DAC B on
DAC A off
DAC A on
Disabled
Enabled
Cb clocked on rising edge
Y clocked on rising edge
Only for PS dual edge clk mode
Only for PS interleaved input at
27 MHz
Must be set if the phase
Only if two input clocks are used
delay between the two input
clocks is <9.25 ns or
>27.75 ns.
SD input only
38h
PS input only
HDTV input only
SD and PS [20-bit]
SD and PS [10-bit]
SD and HDTV [SD
oversampled]
SD and HDTV [HDTV
oversampled]
PS only [at 54 MHz]
10-bit data on S bus
SD Mode 10-bit/20-bit Modes
10-bit data on Y bus
–18–
REV. A
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