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ADV7189 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7189 Multiformat SDTV Video Decoder ADI
Analog Devices ADI
ADV7189 Datasheet PDF : 104 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV7189
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
VS 1
HS 2
DGND 3
DVDDIO 4
P15 5
P14 6
P13 7
P12 8
DGND 9
DVDD 10
NC 11
SFL 12
NC 13
DGND 14
DVDDIO 15
NC 16
P11 17
P10 18
P9 19
P8 20
ADV7189
TOP VIEW
(Not to Scale)
60 AIN5
59 AIN11
58 AIN4
57 AIN10
56 AGND
55 CAP C2
54 CAP C1
53 AGND
52 CML
51 REFOUT
50 AVDD
49 CAP Y2
48 CAP Y1
47 AGND
46 AIN3
45 AIN9
44 AIN2
43 AIN8
42 AIN1
41 AIN7
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
NC = NO CONNECT
Figure 5. 80-Lead LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic Type
3, 9, 14, 31, 71 DGND
G
39, 40, 47, 53, AGND
G
56
4, 15
DVDDIO
P
10, 30, 72
DVDD
P
50
AVDD
P
38
PVDD
P
41–46, 57–62 AIN1–AIN12 I
11, 13, 16, 25, NC
63, 65, 69, 70,
77, 78
5–8, 17–24,
P0–P19
O
32–35, 73–76
2
HS
O
1
VS
O
80
FIELD
O
67
SDA
I/O
68
SCLK
I
66
ALSB
I
64
RESET
I
27
LLC1
O
26
LLC2
O
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
No Connect Pins.
Video Pixel Output Port.
HS is a horizontal synchronization output signal.
VS is a vertical synchronization output signal.
FIELD is a field synchronization output signal.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).
This pin selects the I2C address for the ADV7189. ALSB set to a Logic 0 sets the address for a
write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to reset
the ADV7189 circuitry.
This is a line-locked output clock for the pixel data output by the ADV7189. Nominally 27 MHz,
but varies up or down according to video line length.
This is a divide-by-2 version of the LLC1 output clock for the pixel data output by the ADV7189.
Nominally 13.5 MHz, but varies up or down according to video line length.
Rev. A | Page 11 of 104
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