ADV7184BSTZ View Datasheet(PDF) - Analog Devices

Part Name

Description

View to exact match

ADV7184BSTZ

Multiformat SDTV Video Decoder with Fast Switch Overlay Support

Analog Devices 

Pin No.

67

68

66

64

27

26

29

28

36

79

37

12

51

52

48, 49

54, 55

ADV7184

Mnemonic

SDA

SCLK

ALSB

RESET

LLC1

LLC2

XTAL

XTAL1

PWRDN

OE

ELPF

SFL

REFOUT

CML

CAPY1, CAPY2

CAPC1, CAPC2

Type

I/O

I

I

I

O

O

I

O

I

I

I

O

O

O

I

I

Function

I2C Port Serial Data Input/Output Pin.

I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).

This pin selects the I2C address for the ADV7184. ALSB set to Logic 0 sets the address for a

write as 0x40; set to Logic 1 sets the address as 0x42.

System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to

reset the ADV7184 circuitry.

Line-Locked Clock 1. Line-locked output clock for the pixel data output by the ADV7184.

Nominally 27 MHz, but varies up or down according to video line length.

Line-Locked Clock 2. This is a divide-by-2 version of the LLC1 output clock for the pixel data

output by the ADV7184. Nominally 13.5 MHz, but varies up or down according to video

line length.

This is the input pin for the 28.63636 MHz crystal, or can be overdriven by an external 3.3 V,

28.63636 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental

crystal.

This pin should be connected to the 28.63636 MHz crystal or left as a no connect if an

external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7184. In crystal

mode, the crystal must be a fundamental crystal.

Logic 0 on this pin places the ADV7184 in a power-down mode. Refer to the I2C Register

Maps section for more options on power-down modes for the ADV7184.

When set to Logic 0, OE enables the pixel output bus, P15 to P0 of the ADV7184.

Logic 1 on the OE pin places P15 through P0, HS, VS, and SFL/SYNC_OUT into a high

impedance state.

The recommended external loop filter must be connected to this ELPF pin, as shown in

Figure 50.

Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to

lock the subcarrier frequency when this decoder is connected to any Analog Devices, Inc.

digital video encoder.

Internal Voltage Reference Output. Refer to Figure 50 for a recommended capacitor

network for this pin.

The CML pin is a common-mode level for the internal ADCs. Refer to Figure 50 for a

recommended capacitor network for this pin.

ADC’s Capacitor Network. Refer to Figure 50 for a recommended capacitor network for

these pins.

ADC’s Capacitor Network. Refer to Figure 50 for a recommended capacitor network for

these pins.

Rev. 0 | Page 11 of 108

Share Link: