ADV7181DWBCPZ View Datasheet(PDF) - Analog Devices
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Description
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ADV7181DWBCPZ
Analog Devices
ADV7181DWBCPZ Datasheet PDF : 24 Pages
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Data Sheet
ADV7181D
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C,
unless otherwise noted. The minimum and maximum specifications are guaranteed over this temperature range.
Table 4.
Parameter1
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
Horizontal Sync Input Frequency
LLC Frequency Range
I2C PORT2
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDATA Setup Time
SCLK and SDATA Rise Time
SCLK and SDATA Fall Time
Setup Time (Stop Condition)
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark-Space Ratio
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9:t10
Description
Min
14.8
12.825
0.6
1.3
0.6
0.6
100
5
45:55
Typ
Max
28.63636
±50
110
75
400
300
300
0.6
55:45
DATA AND CONTROL OUTPUTS
Data Output Transition Time
SDR (SDP)3
t11
Negative clock edge to start of valid data
3.6
t12
End of valid data to negative clock edge
2.4
SDR (CP)4
t13
End of valid data to negative clock edge
2.8
t14
Negative clock edge to start of valid data
0.1
DDR (CP)4, 5
t15
Positive clock edge to end of valid data −4 + TLLC/4
t16
Positive clock edge to start of valid data 0.25 + TLLC/4
t17
Negative clock edge to end of valid data −2.95 + TLLC/4
t18
Negative clock edge to start of valid data −0.5 + TLLC/4
Unit
MHz
ppm
kHz
MHz
kHz
μs
μs
μs
μs
ns
ns
ns
μs
ms
% duty
cycle
ns
ns
ns
ns
ns
ns
ns
ns
1 Guaranteed by characterization.
2 TTL input values are 0 V to 3 V, with rise/fall times of ≤3 ns, measured between the 10% and 90% points.
3 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
4 CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.
5 DDR timing specifications dependent on LLC output pixel clock; TLLC/4 = 9.25 ns at LLC = 27 MHz.
Timing Diagrams
t3
SDATA
t5
t3
SCLK
t6
t1
t2
t7
t4
t8
Figure 2. I2C Timing
Rev. 0 | Page 7 of 24
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