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ADV7181DBCPZ View Datasheet(PDF) - Analog Devices

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Description
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ADV7181DBCPZ Datasheet PDF : 24 Pages
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ADV7181D
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Data Sheet
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
INT 1
HS/CS 2
GND 3
DVDDIO 4
P15 5
P14 6
P13 7
P12 8
SFL/SYNC_OUT 9
GND 10
DVDDIO 11
P11 12
P10 13
P9 14
P8 15
P7 16
PIN 1
ADV7181D
TOP VIEW
(Not to Scale)
48 AIN9
47 AIN8
46 AIN7
45 AIN6
44 CAPC2
43 CML
42 REFOUT
41 AVDD
40 CAPY2
39 CAPY1
38 AIN5
37 AIN4
36 AIN3
35 AIN2
34 AIN1
33 SOG
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO GND.
Figure 6. Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
Type
1
INT
Output
2
HS/CS
Output
3, 10, 24, 57
4, 11
28 to 25, 19 to 12,
8 to 5, 62 to 59
9
GND
DVDDIO
P0 to P19
SFL/SYNC_OUT
Ground
Power
Output
Output
20
21
22
23, 58
29
30
31
32
LLC
XTAL1
XTAL
DVDD
PWRDWN
ELPF
PVDD
FB
Output
Output
Input
Power
Input
Output
Power
Input
Description
Interrupt. This pin can be active low or active high. When SDP/CP status bits change,
this pin is triggered. The set of events that triggers an interrupt is under user control.
Horizontal Synchronization Output Signal (HS). Available in SDP and CP modes.
Digital Composite Synchronization Signal (CS). Available in CP mode only.
Ground.
Digital I/O Supply Voltage (3.3 V).
Video Pixel Output Port. See Table 10 and Table 11 for output configuration modes.
Subcarrier Frequency Lock (SFL). This pin contains a serial output stream that can be
used to lock the subcarrier frequency when this decoder is connected to any Analog
Devices digital video encoder.
Sliced Synchronization Output Signal (SYNC_OUT). Available in CP mode only.
Line-Locked Clock Output for Pixel Data. The range is 12.825 MHz to 75 MHz.
This pin should be connected to the 28.63636 MHz crystal or left unconnected if an
external 3.3 V, 28.63636 MHz clock oscillator source is used to clock the ADV7181D.
In crystal mode, the crystal must be a fundamental crystal.
Input Pin for the 28.63636 MHz Crystal. This input can be overdriven by an external
3.3 V, 28.63636 MHz clock oscillator source to clock the ADV7181D.
Digital Core Supply Voltage (1.8 V).
Power-Down Input. A Logic 0 on this pin places the ADV7181D in power-down mode.
External Loop Filter Output. The recommended external loop filter must be connected
to this pin (see the Recommended External Loop Filter Components section).
PLL Supply Voltage (1.8 V).
Fast Blank Input. Fast switch between CVBS and RGB analog signals.
Rev. 0 | Page 10 of 24
 

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