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ADV7181C View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7181C 10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer ADI
Analog Devices ADI
ADV7181C Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV7181C
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
INT 1
HS/CS 2
DGND 3
DVDDIO 4
P15 5
P14 6
P13 7
P12 8
SFL/SYNC_OUT 9
DGND 10
DVDDIO 11
P11 12
P10 13
P9 14
P8 15
P7 16
PIN 1
ADV7181C
TOP VIEW
(Not to Scale)
48 AIN5
47 AIN4
46 AIN3
45 NC
44 CAPC2
43 AGND
42 CML
41 REFOUT
40 AVDD
39 CAPY2
38 CAPY1
37 AGND
36 AIN2
35 AIN1
34 FB
33 NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NOTES
1. NC = NO CONNECT.
2. THE LFCSP_VQ HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
3, 10, 24, 57
DGND
32, 37, 43
AGND
4, 11
DVDDIO
23, 58
DVDD
40
AVDD
31
PVDD
34
FB
35, 36, 46, 47, 48, 49
AIN1 to AIN6
28 to 25, 19 to 12,
8 to 5, 62 to 59
P0 to P19
1
INT
2
HS/CS
64
VS
63
FIELD/DE
53
SDATA
54
SCLK
52
ALSB
Figure 2. Pin Configuration
Type 1
G
G
P
P
P
P
I
I
O
Description
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Fast Switch Overlay Input. This pin switches between CVBS and RGB analog signals.
Analog Video Input Channels.
Video Pixel Output Port. Refer to Table 10 for output configuration modes.
O
Interrupt. This pin can be active low or active high. When SDP/CP status bits
change, this pin is triggered. The set of events that triggers an interrupt is
under user control.
O
HS: Horizontal Synchronization Output Signal (SDP and CP Modes).
CS: Digital Composite Synchronization Signal (CP Mode).
O
Vertical Synchronization Output Signal (SDP and CP Modes).
O
Field Synchronization Output Signal (All Interlaced Video Modes). This pin also
can be enabled as an data enable signal (DE) in CP mode to allow direct
connection to a HDMI/DVI Tx IC.
I/O
I2C Port Serial Data Input/Output Pin.
I
I2C Port Serial Clock Input. Maximum clock rate of 400 kHz.
I
This pin selects the I2C address for the ADV7181C control and VBI readback
ports. ALSB set to Logic 0 sets the address for a write to Control Port 0x40 and
the readback address for VBI Port 0x21. ALSB set to a Logic 1 sets the address
for a write to Control Port 0x42 and the readback address for VBI Port 0x23.
Rev. 0 | Page 9 of 20
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