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ADV7181WBCPZ View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7181WBCPZ 10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer ADI
Analog Devices ADI
ADV7181WBCPZ Datasheet PDF : 20 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7181C
TIMING CHARACTERISTICS
AVDD = 3.15 V to 3.45 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 3.0 V to 3.6 V, PVDD = 1.71 V to 1.89 V. TMIN to TMAX = −40°C to +85°C,
unless otherwise noted.
Table 3.
Parameter1, 2
SYSTEM CLOCK AND CRYSTAL
Crystal Nominal Frequency
Crystal Frequency Stability
LLC Frequency Range3
I2C PORT4
SCLK Frequency
SCLK Min Pulse Width High
SCLK Min Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Time
SCLK and SDA Fall Time
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA and CONTROL OUTPUTS
Data Output Transition Time SDR (SDP)5
Data Output Transition Time SDR (SDP)5
Data Output Transition Time SDR (CP)6
Data Output Transition Time SDR (CP)6
Data Output Transition Time DDR (CP)6, 7
Data Output Transition Time DDR (CP)6, 7
Data Output Transition Time DDR (CP)6, 7
Data Output Transition Time DDR (CP)6, 7
Symbol Test Conditions
Min
12.825
t1
0.6
t2
1.3
t3
0.6
t4
0.6
t5
100
t6
t7
t8
5
t9:t10
45:55
t11
Negative clock edge
to start of valid data
t12
End of valid data to
negative clock edge
t13
End of valid data to
negative clock edge
t14
Negative clock edge
to start of valid data
t15
Positive clock edge to −4 + TLLC/4
end of valid data
t16
Positive clock edge to 0.25 + TLLC/4
start of valid data
t17
Negative clock edge −2.95 + TLLC/4
to end of valid data
t18
Negative clock edge −0.5 + TLLC/4
to start of valid data
Typ
Max Unit
28.63636
MHz
±50 ppm
110 MHz
400 kHz
μs
μs
μs
μs
ns
300 ns
300 ns
0.6
μs
ms
55:45 % duty cycle
3.6 ns
2.4 ns
2.8 ns
0.1 ns
ns
ns
ns
ns
1 The minimum/maximum specifications are guaranteed over this range.
2 Guaranteed by characterization.
3 Maximum LLC frequency is 110 MHz.
4 TTL input values are 0 V to 3 V, with rise/fall times of 3 ns, measured between the 10% and 90% points.
5 SDP timing figures obtained using default drive strength value (0xD5) in Register Subaddress 0xF4.
6 CP timing figures obtained using maximum drive strength value (0xFF) in Register Subaddress 0xF4.
7 DDR timing specifications dependent on LLC output pixel clock; TLCC/4 = 9.25 ns at LLC = 27 MHz.
Rev. 0 | Page 6 of 20
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