ADV7181CBSTZ-REEL View Datasheet(PDF) - Analog Devices

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Description

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ADV7181CBSTZ-REEL

10-Bit, Integrated, Multiformat SDTV Video Decoder and RGB Graphics Digitizer

Analog Devices 

ADV7181C

On the ADV7181C, it is recommended to use the ADC mapping shown in Table 8.

Table 8. Recommended ADC Mapping

Mode

Required ADC Mapping

CVBS

ADC0

YC/YC auto

Y = ADC0

C = ADC1

Component YUV

Y = ADC0

U = ADC2

V = ADC1

Component YUV

Y = ADC0

U = ADC2

V = ADC1

SCART RGB

Graphics

RGB Mode

CBVS = ADC0

G = ADC1

B = ADC3

R = ADC2

G = ADC0

B = ADC2

R = ADC1

AIN Channel

CVBS = AIN1

Y = AIN2

C = AIN3

Y = AIN6

U = AIN4

V = AIN5

Y = AIN6

U = AIN4

V = AIN5

CVBS = AIN2

G = AIN6

B = AIN4

R = AIN5

G = AIN6

B = AIN4

R = AIN5

Core

SD

SD

SD

CP

SD

CP

Configuration1

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

INSEL[3:0] = 0000

SDM_SEL[1:0] = 11

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

INSEL[3:0] = 1001

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 1010

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0000

VID_STD[3:0] = 0010

INSEL[3:0] = 0000

SDM_SEL[1:0] = 00

PRIM_MODE[3:0] = 0001

VID_STD[3:0] = 1100

1 Configuration to format follow-on blocks in correct format.

Table 9. Manual MUX Settings for All ADCs

ADC0_SW_SEL[3:0]

0001

0010

0100

0101

0110

1100

ADC0

Connection

AIN1

AIN2

AIN4

AIN5

AIN6

AIN3

ADC1_SW_SEL[3:0]

0001

0010

0100

0101

0110

1100

ADC_SWITCH_MAN to 1

ADC1

Connection ADC2_SW_SEL[3:0]

N/A

0001

N/A

0010

AIN4

0100

AIN5

0101

AIN6

0110

AIN3

1100

ADC2

Connection

N/A

AIN2

AIN4

AIN5

AIN6

N/A

ADC3_SW_SEL[3:0]

0001

0010

0100

0101

0110

1100

ADC3

Connection

N/A

N/A

AIN4

N/A

N/A

N/A

The analog input muxes of the ADV7181C must be controlled

directly. This is referred to as manual input muxing. The manual

muxing is activated by setting the ADC_SWITCH_MAN bit

(see Table 9). It affects only the analog switches in front of the

ADCs. INSEL, SDM_SEL, PRIM_MODE, and VID_STD still

have to be set so that the follow-on blocks process the video

data in the correct format.

Not every input pin can be routed to any ADC. There are

restrictions in the channel routing imposed by the analog

signal routing inside the IC. See Table 9 for an overview of

the routing capabilities inside the chip. The three mux

sections can be controlled by the reserved control signal

buses ADC0_SW[3:0]/ ADC1_SW[3:0]/ADC2_SW[3:0].

Table 9 explains the ADC mapping configuration for the

following:

• ADC_SWITCH_MAN, manual input muxing enable,

IO map, Address 0C[7]

• ADC0_SW[3:0], ADC0 mux configuration, IO map,

Address 0D[3:0]

• ADC1_SW[3:0], ADC1 mux configuration, IO map,

Address 0D[7:4]

• ADC2_SW[3:0], ADC2 mux configuration, IO map,

Address 0E[3:0]

• ADC3_SW[3:0], ADC3 mux configuration, IO map,

Address 0E[7:4]

Rev. 0 | Page 15 of 20

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