ADV7181B View Datasheet(PDF) - Analog Devices
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ADV7181B Datasheet PDF : 96 Pages
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ADV7181B
GLOBAL CONTROL REGISTERS
Register control bits listed in this section affect the whole chip.
POWER-SAVE MODES
Power-Down
PDBP, Address 0x0F [2]
The digital core of the ADV7181B can be shut down by using a
pin (PWRDN) and a bit (PWRDN see below). The PDBP
controls which of the two has the higher priority. The default is
to give the pin (PWRDN) priority. This allows the user to have
the ADV7181B powered down by default.
When PDBD is 0 (default), the digital core power is controlled
by the PWRDN pin (the bit is disregarded).
When PDBD is 1, the bit has priority (the pin is disregarded).
PWRDN, Address 0x0F [5]
Setting the PWRDN bit switches the ADV7181B into a chip-
wide power-down mode. The power-down stops the clock from
entering the digital section of the chip, thereby freezing its
operation. No I2C bits are lost during power-down. The
PWRDN bit also affects the analog blocks and switches them
into low current modes. The I2C interface itself is unaffected,
and remains operational in power-down mode.
The ADV7181B leaves the power-down state if the PWRDN bit
is set to 0 (via I2C), or if the overall part is reset using the
RESET pin.
PDBP must be set to 1 for the PWRDN bit to power down the
ADV7181B.
When PWRDN is 0 (default), the chip is operational.
When PWRDN is 1, the ADV7181B is in chip-wide power-down.
ADC Power-Down Control
The ADV7181B contains three 9-bit ADCs (ADC 0, ADC 1, and
ADC 2). If required, it is possible to power down each ADC
individually.
When should the ADCs be powered down?
• CVBS mode. ADC 1 and ADC 2 should be powered down
to save on power consumption.
• S-Video mode. ADC 2 should be powered down to save on
power consumption.
PWRDN_ADC_0, Address 0x3A [3]
When PWRDN_ADC_0 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_0 is 1, ADC 0 is powered down.
PWRDN_ADC_1, Address 0x3A [2]
When PWRDN_ADC_1 is 0 (default), the ADC is in normal
operation.
When PWRDN_ADC_1 is 1, ADC 1 is powered down.
PWRDN_ADC_2, Address 0x3A [1]
When PWRDN_ADC_2 is 0 (default), the ADC is in normal
operation (default).
When PWRDN_ADC_2 is 1, ADC 2 is powered down.
RESET CONTROL
Chip Reset (RES), Address 0x0F [7]
Setting this bit, equivalent to controlling the RESET pin on the
ADV7181B, issues a full chip reset. All I2C registers are reset to
their default values. Note that some register bits do not have a
reset value specified. They keep their last written value. Those
bits are marked as having a reset value of x in the register table.
After the reset sequence, the part immediately starts to acquire
the incoming video signal.
After setting the RES bit (or initiating a reset via the pin), the
part returns to the default mode of operation with respect to its
primary mode of operation. All I2C bits are loaded with their
default values, making this bit self-clearing.
Executing a software reset takes approximately 2 ms. However, it
is recommended to wait 5 ms before any further I2C writes are
performed.
The I2C master controller receives a no acknowledge condition
on the ninth clock cycle when chip reset is implemented. See the
MPU Port Description section.
When RES is 0 (default), operation is normal.
When RES is 1, the reset sequence starts.
Rev. 0 | Page 14 of 96
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