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ADV7181BBCPZ View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7181BBCPZ Multiformat SDTV Video Decoder ADI
Analog Devices ADI
ADV7181BBCPZ Datasheet PDF : 96 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
Pin No.
21
29
30
9
41
42
38, 39
44
ADV7181B
Mnemonic
XTAL1
PWRDN
ELPF
SFL
REFOUT
CML
CAPY1, CAPY2
CAPC2
Type
O
I
I
O
O
O
I
I
Function
This pin should be connected to the 27 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7181B. In crystal mode, the
crystal must be a fundamental crystal.
A logic low on this pin places the ADV7181B in a power-down mode. Refer to the I2C
Register Maps section for more options on power-down modes for the ADV7181B.
The recommended external loop filter must be connected to this ELPF pin, as shown in
Figure 44.
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital
video encoder.
Internal Voltage Reference Output. Refer to Figure 44 for a recommended capacitor
network for this pin.
The CML pin is a common-mode level for the internal ADCs. Refer to Figure 44 for a
recommended capacitor network for this pin.
ADC’s Capacitor Network. Refer to Figure 44 for a recommended capacitor network for
this pin.
ADC’s Capacitor Network. Refer to Figure 44 for a recommended capacitor network for
this pin.
Rev. 0 | Page 11 of 96
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