ADV7181 View Datasheet(PDF) - Analog Devices
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ADV7181 Datasheet PDF : 104 Pages
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ADV7181
PVENDDELE PAL VSync End Delay on Even Field,
Address 0xE9,[6]
Table 128. PVENDDELE Function
PVENDDELE Description
0*
No delay.
1
Delay VSync going low on an even field by a line
relative to PVEND.
*Default value.
PVENDSIGN PAL VSync End Sign, Address 0xE9, [5]
Table 129. PVENDSIGN Function
PVENDSIGN Description
0*
Delay end of VSync. Set for user manual
programming.
1
Advance end of VSync. Not recommended for
user programming.
*Default value.
PVEND[4:0] PAL Vsync End, Address 0xE9,[4:0]
Table 130. PVEND Function
PVEND
Description
10100*
PAL VSync end position.
*Default value.
Note: For all NTSC/PAL VSync timing controls, both the V bit
in the AV code and the VSync on the VS pin are modified.
PFTOGDELO PAL Field Toggle Delay on Odd Field,
Address 0xEA, [7]
Table 131. PFTOGDELO Function
PFTOGDELO Description
0*
No delay.
1
Delay F toggle/transition on an odd field by a
line relative to PFTOG.
*Default value.
PFTOGDELE PAL Field Toggle Delay on Even Field,
Address 0xEA [6]
Table 132. PFTOGDELE Function
PFTOGDELE Description
0
No delay.
1*
Delay F toggle/transition on an even field by a
line relative to PFTOG.
*Default value.
PFTOGSIGN PAL Field Toggle Sign, Address 0xEA, [5]
Table 133. PFTOGSIGN Function
PFTOGSIGN Description
0
Delay Field transition. Set for user manual
programming.
1*
Advance Field transition. Not recommended for
user programming.
*Default value.
PFTOG PAL Field Toggle, Address 0xEA [4:0]
Table 134. PFTOG Function
PFTOG
Description
00011*
PAL Field toggle position.
*Default value.
For all NTSC/PAL Field timing controls, the F bit in the AV
code and the Field signal on the FIELD/DE pin are modified.
1
PFTOGSIGN
0
ADVANCE TOGGLE OF
FIELD BY PTOG[4:0]
DELAY TOGGLE OF
FIELD BY PFTOG[4:0]
NOT VALID FOR USER
PROGRAMMING
ODD FIELD?
YES
NO
PFTOGDELO
1
0
ADDITIONAL
DELAY BY
1 LINE
PFTOGDELE
0
1
ADDITIONAL
DELAY BY
1 LINE
FIELD
TOGGLE
Figure 29. PAL F Toggle
SDP SYNC PROCESSING
The ADV7181 has two additional sync processing blocks that
postprocess the raw synchronization information extracted
from the digitized input video. If desired, the blocks can be
disabled via the following two I2C bits.
ENHSPLL Enable HSync Processor (SDP), Address 0x01, [6]
The HSYNC processor is designed to filter incoming HSyncs
that have been corrupted by noise, providing improved per-
formance for video signals with stable time bases but poor SNR.
For CVBS PAL/NTSC, YC PAL/NTSC enable the HSync
processor. For SECAM disable the HSync Processor. For YPrPb
through SDP, disable HSYNC Processor.
Table 135. ENHSPLL Function
ENHSPLL
Description
0
Disable the HSync processor.
1*
Enable the HSync processor.
*Default value.
Rev. A | Page 50 of 104
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