ADV7181BCP View Datasheet(PDF) - Analog Devices

Part Name

Description

View to exact match

ADV7181BCP

Multiformat SDTV Video Decoder

Analog Devices 

SDP SYNC PROCESSING

The SDP extracts syncs embedded in the video data stream.

There is currently no support for external HS/VS inputs. The

sync extraction has been optimized to support imperfect video

sources (e.g., videocassette recorders with head switches). The

actual algorithm used employs a coarse detection based on a

threshold crossing followed by a more detailed detection using

an adaptive interpolation algorithm. The raw sync information

is sent to a line-length measurement and prediction block. The

output of this is then used to drive the digital resampling

section to ensure that the SDP outputs 720 active pixels per line.

The sync processing on the ADV7181 also includes two

specialized postprocessing blocks that filter and condition the

raw sync information retrieved from the digitized analog video.

• VSYNC Processor. This block provides extra filtering of the

detected VSYNCs to give improved vertical lock.

• HSYNC Processor. The HSYNC processor is designed to

filter incoming HSYNCs that have been corrupted by

noise, providing much improved performance for video

signals with stable time base but poor SNR.

SDP VBI DATA RECOVERY

The SDP can retrieve the following information from the input

video:

• Wide-screen signaling (WSS)

• Copy generation management system (CGMS)

• Closed caption (CC)

• Macrovision protection presence

• EDTV data

• Gemstar compatible data slicing

The SDP is also capable of automatically detecting the incoming

video standard with respect to

• Color subcarrier frequency

• Field rate

• Line rate

and can configure itself to support PAL-BGHID, PAL-M/N,

PAL-combination N, NTSC-M, NTSC-J, SECAM 50 Hz/60 Hz,

NTSC4.43, and PAL60.

ADV7181

SDP GENERAL SETUP

Video Standard Selection (SDP)

The VID_SEL[3:0] register allows the user to force the digital

core into a specific video standard. Under normal

circumstances, this should not be necessary. The VID_SEL[3:0]

bits default to an autodetection mode that supports PAL, NTSC,

SECAM, and variants thereof.

Refer to the Autodetection of SDP Modes section for more

information on the autodetection system.

Autodetection of SDP Modes

In order to guide the autodetect system of the SDP block,

individual enable bits are provided for each of the supported

video standards. Setting the relevant bit to 0 inhibits the

standard from being detected automatically. Instead, the system

picks the closest of the remaining enabled standards. The results

of SDP autodetection can be read back via the status registers.

See the Global Status Registers section for more information.

Table 29. VID_SEL Function

VID_SEL[3:0]

Address 0x00 [7:4] Description

0000*

Autodetect (PAL BGHID) <–> NTSC J.

0001

Autodetect (PAL BGHID) <–> NTSC M.

0010

Autodetect (PAL N) <–> NTSC J.

0011

Autodetect (PAL N) <–> NTSC M.

0100

NTSC J (1)

0101

NTSC M (1).

0110

PAL 60.

0111

NTSC 4.43 (1).

1000

PAL BGHID.

1001

PAL N (= PAL BGHID (with pedestal)).

1010

PAL M (without pedestal).

1011

PAL M.

1100

PAL combination N.

1101

PAL combination N (with pedestal).

1110

SECAM.

1111

SECAM (with pedestal).

*Default value.

AD_SEC525_EN Enable Autodetection of SECAM 525 line

video (SDP), Address 0x07, [7]

Table 30. AD_SEC525_EN Function

AD_SEC525_EN Description

0*

Disable the autodetection of a 525-line

system with a SECAM style, FM-modulated

color component.

1

Enable the detection.

*Default value.

Rev. A | Page 21 of 104

Share Link: