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ADV7181BCP View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7181BCP Multiformat SDTV Video Decoder ADI
Analog Devices ADI
ADV7181BCP Datasheet PDF : 104 Pages
First Prev 11 12 13 14 15 16 17 18 19 20 Next Last
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
ADV7181
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
NC 1
HS 2
DGND 3
DVDDIO 4
P11 5
P10 6
P9 7
P8 8
SFL 9
DGND 10
DVDDIO 11
NC 12
NC 13
P7 14
P6 15
P5 16
PIN 1
INDICATOR
ADV7181
TOP VIEW
(Not to Scale)
48 AIN5
47 AIN4
46 AIN3
45 AGND
44 CAPC2
43 AGND
42 CML
41 REFOUT
40 AVDD
39 CAPY2
38 CAPY1
37 AGND
36 AIN2
35 AIN1
34 DGND
33 NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
Figure 4. 64-Lead LFCSP/LQFP Pin Configuration
Table 7. Pin Function Descriptions
Pin No.
Mnemonic
3, 10, 24, 34, 57
DGND
32, 37, 43, 45
AGND
4, 11
DVDDIO
25, 58
DVDD
40
AVDD
31
PVDD
35, 36, 46–49
AIN1–AIN6
1, 12, 13, 27, 28, 33, NC
50, 55, 56
5–8, 14–19, 25, 26, P0–P15
59–62
2
HS
64
VS
63
FIELD
53
SDA
54
SCLK
52
ALSB
51
RESET
20
LLC
22
XTAL
21
XTAL1
29
PWRDN
Type
G
G
P
P
P
P
I
O
O
O
O
I/O
I
I
I
O
I
O
I
Function
Digital Ground.
Analog Ground.
Digital I/O Supply Voltage (3.3 V).
Digital Core Supply Voltage (1.8 V).
Analog Supply Voltage (3.3 V).
PLL Supply Voltage (1.8 V).
Analog Video Input Channels.
No Connect Pins.
Video Pixel Output Port.
HS is a horizontal synchronization output signal.
VS is a vertical synchronization output signal.
FIELD is a field synchronization output signal.
I2C Port Serial Data Input/Output Pin.
I2C Port Serial Clock Input (Max Clock Rate of 400 kHz).
This pin selects the I2C address for the ADV7181. ALSB set to a Logic 0 sets the address for a
write as 0x40; for ALSB set to a logic high, the address selected is 0x42.
System Reset Input, Active Low. A minimum low reset pulse width of 5 ms is required to
reset the ADV7181 circuitry.
This is a line-locked output clock for the pixel data output by the ADV7181. Nominally
27 MHz, but varies up or down according to video line length.
This is the input pin for the 27 MHz crystal, or can be overdriven by an external 3.3 V,
27 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental crystal.
This pin should be connected to the 27 MHz crystal or left as a no connect if an external
3.3 V, 27 MHz clock oscillator source is used to clock the ADV7181. In crystal mode, the
crystal must be a fundamental crystal.
A logic low on this pin places the ADV7181 in a power-down mode. Refer to the I2C Control
Register Map section for more options on power-down modes for the ADV7181.
Rev. A | Page 11 of 104
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