datasheetbank_Logo     Integrated circuits, Transistor, Semiconductors Search and Datasheet PDF Download Site

ADV7123KSTZ50 View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7123KSTZ50 CMOS, 330 MHz Triple 10-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7123KSTZ50 Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7123
Parameter
Total Harmonic Distortion
fCLK = 50 MHz; fOUT = 1.00 MHz
TA = 25°C
TMIN to TMAX
fCLK = 50 MHz; fOUT = 2.00 MHz
fCLK = 100 MHz; fOUT = 2.00 MHz
fCLK = 140 MHz; fOUT = 2.00 MHz
DAC PERFORMANCE
Glitch Impulse
DAC-to-DAC Crosstalk3
Data Feedthrough4, 5
Clock Feedthrough4, 5
Min
Typ
Max
Unit
66
dBc
65
dBc
64
dBc
64
dBc
55
dBc
10
pV-sec
23
dB
22
dB
33
dB
1 These maximum/minimum specifications are guaranteed by characterization over the 3.0 V to 3.6 V range.
2 Note that the ADV7123 exhibits high performance when operating with an internal voltage reference, VREF.
3 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions.
4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough.
5 TTL input values are 0 V to 3 V, with input rise/fall times of −3 ns, measured at the 10% and 90% points. Timing reference points are 50% for inputs and outputs.
5 V TIMING SPECIFICATIONS
VAA = 5 V ± 5%,1 VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,2 unless otherwise noted, TJ MAX = 110°C.
Table 5.
Parameter3
ANALOG OUTPUTS
Analog Output Delay
Analog Output Rise/Fall Time4
Analog Output Transition Time5
Analog Output Skew6
CLOCK CONTROL
CLOCK Frequency7
Data and Control Setup
Data and Control Hold
CLOCK Period
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
CLOCK Pulse Width High
CLOCK Pulse Width Low
Pipeline Delay6
PSAVE Up Time6
Symbol
t6
t7
t8
t9
fCLK
t1
t2
t3
t4
t5
t4
t5
t4
t5
tPD
t10
Min
0.5
0.5
0.5
0.5
1.5
4.17
1.875
1.875
2.85
2.85
8.0
8.0
1.0
Typ Max
5.5
1.0
15
1
2
50
140
240
1.0 1.0
2
10
Unit
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock cycles
ns
Conditions
50 MHz grade
140 MHz grade
240 MHz grade
fCLK_MAX = 240 MHz
fCLK_MAX = 240 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 140 MHz
fCLK_MAX = 50 MHz
fCLK_MAX = 50 MHz
1 These maximum and minimum specifications are guaranteed over this range.
2 Temperature range: TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz.
3 Timing specifications are measured with input levels of 3.0 V (VIH) and 0 V (VIL) 0 for both 5 V and 3.3 V supplies.
4 Rise time was measured from the 10% to 90% point of zero to full-scale transition, fall time from the 90% to 10% point of a full-scale transition.
5 Measured from 50% point of full-scale transition to 2% of final value.
6 Guaranteed by characterization.
7 fCLK maximum specification production tested at 125 MHz; 5 V limits specified here are guaranteed by characterization.
Rev. D | Page 7 of 24
Direct download click here

 

Share Link : 

All Rights Reserved © datasheetbank.com 2014 - 2020 [ Privacy Policy ] [ Request Datasheet ] [ Contact Us ]