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ADV7123JSTZ240-RL View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7123JSTZ240-RL CMOS, 330 MHz Triple 10-Bit High Speed Video DAC ADI
Analog Devices ADI
ADV7123JSTZ240-RL Datasheet PDF : 24 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
ADV7123
SPECIFICATIONS
5 V SPECIFICATIONS
VAA = 5 V ± 5%, VREF = 1.235 V, RSET = 560 Ω, CL = 10 pF. All specifications TMIN to TMAX,1 unless otherwise noted, TJ MAX = 110°C.
Table 1.
Parameter
STATIC PERFORMANCE
Resolution (Each DAC)
Integral Nonlinearity (BSL)
Differential Nonlinearity
DIGITAL AND CONTROL INPUTS
Input High Voltage, VIH
Input Low Voltage, VIL
Input Current, IIN
PSAVE Pull-Up Current
Input Capacitance, CIN
ANALOG OUTPUTS
Output Current
DAC-to-DAC Matching
Output Compliance Range, VOC
Output Impedance, ROUT
Output Capacitance, COUT
Offset Error
Gain Error2
VOLTAGE REFERENCE, EXTERNAL AND
INTERNAL
Reference Range, VREF
POWER DISSIPATION
Digital Supply Current3
Analog Supply Current
Standby Supply Current4
Power Supply Rejection Ratio
Min
Typ Max
Unit Test Conditions1
10
Bits
−1
±0.4 +1
LSB
−1
±0.25 +1
LSB
Guaranteed Monotonic
2
V
0.8
V
−1
+1
μA
VIN = 0.0 V or VDD
20
μA
10
pF
2.0
2.0
1.0
0
100
10
−0.025
−5.0
26.5
18.5
5
1.4
+0.025
+5.0
mA
mA
%
V
pF
% FSR
% FSR
Green DAC, SYNC = high
RGB DAC, SYNC = low
IOUT = 0 mA
Tested with DAC output = 0 V
FSR = 17.62 mA
1.12
1.235 1.35
V
3.4
9
10.5 15
18
25
67
72
8
2.1
5.0
0.1
0.5
mA
mA
mA
mA
mA
mA
%/%
fCLK = 50 MHz
fCLK = 140 MHz
fCLK = 240 MHz
RSET = 560 Ω
RSET = 4933 Ω
PSAVE = low, digital, and control inputs at VDD
1 Temperature range TMIN to TMAX: −40°C to +85°C at 50 MHz and 140 MHz, 0°C to 70°C at 240 MHz and 330 MHz.
2 Gain error = {(Measured (FSC)/Ideal (FSC) − 1) × 100}, where Ideal = VREF /RSET × K × (0x3FFH) and K = 7.9896.
3 Digital supply is measured with a continuous clock that has data input corresponding to a ramp pattern and with an input level at 0 V and VDD.
4 These maximum/minimum specifications are guaranteed by characterization to be over the 4.75 V to 5.25 V range.
Rev. D | Page 3 of 24
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