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ADV7180WBCPZ-REEL 10-Bit, 4× Oversampling SDTV Video Decoder ADI
Analog Devices ADI
ADV7180WBCPZ-REEL Datasheet PDF : 120 Pages
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ADV7180
POWER-ON RESET
After power-up, it is necessary to execute a reset operation. For
correct operation, RESET should remain asserted/pulled low for
5 ms after power supplies are stable and within specification
and PWRDWN (not available in 32-lead LFCSP) is deasserted/
pulled high.
ANALOG INPUT MUXING
The ADV7180 has an integrated analog muxing section that
allows more than one source of video signal to be connected to
the decoder. Figure 12 and Figure 13 outline the overall structure of
the input muxing provided in the ADV7180.
A maximum of six CVBS inputs can be connected to and
decoded by the 64-lead and 48-lead devices, and a maximum of
three CVBS inputs can be connected to and decoded by the 40-lead
and 32-lead LFCSP devices. As shown in the Pin Configurations
and Function Description section, these analog input pins lie in
close proximity to one another, which requires careful design of
the printed circuit board (PCB) layout. For example, ground
shielding between all signals should be routed through tracks that are
physically close together. It is strongly recommended to connect
any unused analog input pins to AGND to act as a shield.
Data Sheet
MAN_MUX_EN, Manual Input Muxing Enable,
Address 0xC4[7]
To configure the ADV7180 analog muxing section, the user
must select the analog input (AIN1 to AIN6 for the 64-lead LQFP
and 48-lead devices or AIN1 to AIN3 for the 40-lead and 32-lead
LFCSP devices) that is to be processed by the ADC. MAN_MUX_
EN must be set to 1 to enable the following muxing blocks:
MUX0[2:0], ADC Mux Configuration, Address 0xC3[2:0]
MUX1[2:0], ADC Mux Configuration, Address 0xC3[6:4]
MUX2[2:0], ADC Mux Configuration, Address 0xC4[2:0]
The three mux sections are controlled by the signal buses MUX0/
MUX1/MUX2[2:0]. Table 15 explains the control words used.
The input signal that contains the timing information (HS and VS)
must be processed by MUX0. For example, in a Y/C input
configuration, MUX0 should be connected to the Y channel
and MUX1 to the C channel. When one or more muxes are not
used to process video, such as the CVBS input, the idle mux and
associated channel clamps and buffers should be powered down
(see the description of Register 0x3A in Table 107).
Table 15. Manual Mux Settings for the ADC (MAN_MUX_EN Must be Set to 1)
ADC Connected To
ADC Connected To
MUX0[2:0]
LQFP-64 or LFCSP-40 or
LQFP-48
LFCSP-32 MUX1[2:0]
LQFP-64 or LFCSP-40 or
LQFP-48
LFCSP-32
000
No connect No connect 000
No connect No connect
001
AIN1
AIN1
001
No connect No connect
010
AIN2
No connect 010
No connect No connect
011
AIN3
No connect 011
AIN3
No connect
100
AIN4
AIN2
100
AIN4
AIN2
101
AIN5
AIN3
101
AIN5
AIN3
110
AIN6
No connect 110
AIN6
No connect
111
No connect No connect 111
No connect No connect
MUX2[2:0]
000
001
010
011
100
101
110
111
Note the following:
CVBS can only be processed by MUX0.
Y/C can only be processed by MUX0 and MUX1.
YPrPb can only be processed by MUX0, MUX1, and MUX2.
ADC Connected To
LQFP-64 or LFCSP-40 or
LQFP-48
LFCSP-32
No connect No connect
No connect No connect
AIN2
No connect
No connect No connect
No connect No connect
AIN5
AIN3
AIN6
No connect
No connect No connect
Rev. G | Page 20 of 120
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