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ADV7180BCPZ View Datasheet(PDF) - Analog Devices

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ADV7180BCPZ Datasheet PDF : 120 Pages
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Data Sheet
64-LEAD LQFP
ADV7180
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
INTRQ 1
HS 2
DGND 3
DVDDIO 4
P11 5
P10 6
P9 7
P8 8
SFL 9
DGND 10
DVDDIO 11
GPO1 12
GPO0 13
P7 14
P6 15
P5 16
PIN 1
ADV7180
LQFP
TOP VIEW
(Not to Scale)
48 AIN5
47 AIN4
46 AIN3
45 NC
44 NC
43 AGND
42 NC
41 NC
40 AVDD
39 VREFN
38 VREFP
37 AGND
36 AIN2
35 AIN1
34 TEST_0
33 NC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
NC = NO CONNECT
Figure 10. 64-Lead LQFP Pin Configuration
Table 11. 64-Lead LQFP Pin Function Description
Pin No.
Mnemonic Type Description
1
INTRQ
O
Interrupt Request Output. Interrupt occurs when certain signals are detected on the input
video (see Table 108).
2
HS
O
Horizontal Synchronization Output Signal.
3, 10, 24, 57
DGND
G
Digital Ground.
4, 11
DVDDIO
P
Digital I/O Supply Voltage (1.8 V to 3.3 V).
5 to 8, 14 to 19,
25, 26, 59 to 62
P11 to P8,
O
P7 to P2, P1,
P0, P15 to P12
Video Pixel Output Port. See Table 100 for output configuration for 8-bit and 16-bit modes.
9
SFL
O
Subcarrier Frequency Lock. This pin contains a serial output stream that can be used to lock
the subcarrier frequency when this decoder is connected to any Analog Devices digital
video encoder.
12, 13, 55, 56
GPO0 to GPO3 O
General-Purpose Outputs. These pins can be configured via I2C to allow control of external devices.
20
LLC
O
This is a line-locked output clock for the pixel data output by the ADV7180. It is nominally
27 MHz but varies up or down according to video line length.
21
XTAL1
O
This pin should be connected to the 28.6363 MHz crystal or left as a no connect if an external
1.8 V, 28.6363 MHz clock oscillator source is used to clock the ADV7180. In crystal mode,
the crystal must be a fundamental crystal.
22
XTAL
I
This is the input pin for the 28.6363 MHz crystal, or this pin can be overdriven by an external
1.8 V, 28.6363 MHz clock oscillator source. In crystal mode, the crystal must be a fundamental
crystal.
23, 58
DVDD
P
Digital Supply Voltage (1.8 V).
27, 28, 33, 41, 42, NC
44, 45, 50
No Connect. These pins are not connected internally.
29
PWRDWN
I
A logic low on this pin places the ADV7180 in power-down mode.
30
ELPF
I
The recommended external loop filter must be connected to the ELPF pin, as shown in Figure 56.
31
PVDD
P
PLL Supply Voltage (1.8 V).
32, 37, 43
AGND
G
Analog Ground.
34
TEST_0
I
This pin must be tied to DGND.
35, 36, 46 to 49 AIN1 to AIN6
I
Analog Video Input Channels.
Rev. G | Page 15 of 120
 

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