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ADV7180BCPZ-REEL View Datasheet(PDF) - Analog Devices

Part NameDescriptionManufacturer
ADV7180BCPZ-REEL 10-Bit, 4× Oversampling SDTV Video Decoder ADI
Analog Devices ADI
ADV7180BCPZ-REEL Datasheet PDF : 120 Pages
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ADV7180
Data Sheet
TIMING SPECIFICATIONS
Guaranteed by characterization. AVDD = 1.71 V to 1.89 V, DVDD = 1.65 V to 2.0 V, DVDDIO = 1.62 V to 3.6 V, PVDD = 1.65 V to 2.0 V, specified
at operating temperature range, unless otherwise noted.
Table 5.
Parameter
SYSTEM CLOCK AND CRYSTAL
Nominal Frequency
Frequency Stability
I2C PORT
SCLK Frequency
SCLK Minimum Pulse Width High
SCLK Minimum Pulse Width Low
Hold Time (Start Condition)
Setup Time (Start Condition)
SDA Setup Time
SCLK and SDA Rise Times
SCLK and SDA Fall Times
Setup Time for Stop Condition
RESET FEATURE
Reset Pulse Width
CLOCK OUTPUTS
LLC Mark Space Ratio
DATA AND CONTROL OUTPUTS
Data Output Transitional Time
Data Output Transitional Time
Symbol Test Conditions
Min Typ
Max Unit
28.6363
MHz
±50 ppm
400 kHz
t1
0.6
µs
t2
1.3
µs
t3
0.6
µs
t4
0.6
µs
t5
100
ns
t6
300 ns
t7
300 ns
t8
0.6
µs
5
ms
t9:t10
45:55
55:45 % duty cycle
t11
Negative clock edge to start of valid data
(tACCESS = t10 − t11)
t12
End of valid data to negative clock edge
(tHOLD = t9 + t12)
3.6 ns
2.4 ns
Timing Diagrams
t3
t5
t3
SDATA
SCLK
t6
t1
t2
t7
t4
t8
Figure 6. I2C Timing
OUTPUT LLC
t9
t10
OUTPUTS P0 TO P15, VS,
HS, FIELD,
SFL
t11
t12
Figure 7. Pixel Port and Control Output Timing
Rev. G | Page 10 of 120
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