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ADV7180BCPZ-REEL View Datasheet(PDF) - Analog Devices

Part Name
Description
View to exact match
ADV7180BCPZ-REEL
ADI
Analog Devices ADI
ADV7180BCPZ-REEL Datasheet PDF : 120 Pages
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Data Sheet
ADV7180
Address Register
0x4A
Interrupt Status 3
(read only)
User Sub Map
Bit Description
SD_OP_CHNG_Q; SD 60 Hz/50 Hz
frame rate at output
Bit (Shading Indicates
Default State)
76543210
0
1
SD_V_LOCK_CHNG_Q
SD_H_LOCK_CHNG_Q
SD_AD_CHNG_Q; SD autodetect
changed
0
1
0
1
0
1
SCM_LOCK_CHNG_Q; SECAM lock
0
1
PAL_SW_LK_CHNG_Q
0
1
0x4B
0x4C
0x4E
Interrupt Clear 3
(write only)
Interrupt Mask 3
(read/write)
Interrupt Status 4 (read only)
Reserved
xx
SD_OP_CHNG_CLR
0
1
SD_V_LOCK_CHNG_CLR
0
1
SD_H_LOCK_CHNG_CLR
0
1
SD_AD_CHNG_CLR
0
1
SCM_LOCK_CHNG_CLR
0
1
PAL_SW_LK_CHNG_CLR
0
1
Reserved
xx
SD_OP_CHNG_MSK
0
1
SD_V_LOCK_CHNG_MSK
0
1
SD_H_LOCK_CHNG_MSK
0
1
SD_AD_CHNG_MSK
0
1
SCM_LOCK_CHNG_MSK
0
1
PAL_SW_LK_CHNG_MSK
0
1
Reserved
xx
VDP_CCAPD_Q
0
1
Reserved
x
VDP_CGMS_WSS_CHNGD_Q; see
0
0x9C Bit 4 of user sub map to determine
whether interrupt is issued for a
1
change in detected data or for when
data is detected regardless of content
Reserved
x
VDP_GS_VPS_PDC_UTC_CHNG_Q;
0
see 0x9C Bit 5 of User Sub Map to deter-
mine whether interrupt is issued for a
1
change in detected data or for when
data is detected regardless of content
Reserved
x
VDP_VITC_Q
0
1
Reserved
x
Comments
No change in SD signal standard
detected at the output
A change in SD signal standard is
detected at the output
No change in SD VSYNC lock status
SD VSYNC lock status has changed
No change in HSYNC lock status
SD HSYNC lock status has changed
No change in AD_RESULT[2:0] bits in
Status 1 register
AD_RESULT[2:0] bits in Status 1 register
have changed
No change in SECAM lock status
SECAM lock status has changed
No change in PAL swinging burst
lock status
PAL swinging burst lock status has
changed
Not used
Do not clear
Clears SD_OP_CHNG_Q bit
Do not clear
Clears SD_V_LOCK_CHNG_Q bit
Do not clear
Clears SD_H_LOCK_CHNG_Q bit
Do not clear
Clears SD_AD_CHNG_Q bit
Do not clear
Clears SCM_LOCK_CHNG_Q bit
Do not clear
Clears PAL_SW_LK_CHNG_Q bit
Not used
Masks SD_OP_CHNG_Q bit
Unmasks SD_OP_CHNG_Q bit
Masks SD_V_LOCK_CHNG_Q bit
Unmasks SD_V_LOCK_CHNG_Q bit
Masks SD_H_LOCK_CHNG_Q bit
Unmasks SD_H_LOCK_CHNG_Q bit
Masks SD_AD_CHNG_Q bit
Unmasks SD_AD_CHNG_Q bit
Masks SCM_LOCK_CHNG_Q bit
Unmasks SCM_LOCK_CHNG_Q bit
Masks PAL_SW_LK_CHNG_Q bit
Unmasks PAL_SW_LK_CHNG_Q bit
Not used
Closed captioning not detected
Closed captioning detected
CGMS/WSS data is not changed/
not available
CGMS/WSS data is changed/available
Gemstar/PDC/VPS/UTC data is not
changed/not available
Gemstar/PDC/VPS/UTC data is
changed/available
VITC data is not available in the VDP
VITC data is available in the VDP
Notes
These bits can be cleared
and masked by
Register 0x4B and
Register 0x4C, respectively
These bits can be cleared
and masked by Register
0x4F and Register 0x50,
respectively; note that an
interrupt in Register 0x4E
for the CCAP, Gemstar,
CGMS, WSS, VPS, PDC,
UTC, and VITC data uses
the VDP data slicer
Rev. G | Page 101 of 120
 

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